bb75f7e27b
Add direct-link device node support for canoe. This device node is used to program SID configuration by iommu driver. This device shares the iommu domain with normal wlan device. Change-Id: Ia54f3cea8b1bec4b9765413e562192ba22269b57 CRs-Fixed: 4001977
177 lines
4.3 KiB
Plaintext
177 lines
4.3 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interconnect/qcom,canoe.h>
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&tlmm {
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cnss_pins {
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cnss_wlan_en_active: cnss_wlan_en_active {
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mux {
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pins = "gpio16";
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function = "gpio";
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};
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config {
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pins = "gpio16";
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drive-strength = <16>;
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output-high;
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bias-pull-up;
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};
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};
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cnss_wlan_en_sleep: cnss_wlan_en_sleep {
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mux {
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pins = "gpio16";
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function = "gpio";
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};
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config {
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pins = "gpio16";
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drive-strength = <2>;
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output-low;
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bias-pull-down;
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};
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};
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cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
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mux {
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pins = "gpio18";
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function = "wcn_sw_ctrl";
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};
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};
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cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
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mux {
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pins = "gpio19";
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function = "wcn_sw";
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};
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};
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cnss_host_sol_default: cnss_host_sol_default {
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mux {
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pins = "gpio204";
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function = "gpio";
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};
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config {
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pins = "gpio204";
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drive-strength = <4>;
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bias-pull-down;
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};
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};
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};
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};
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&reserved_memory {
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cnss_wlan_mem: cnss_wlan_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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};
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};
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&soc {
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wlan_peach: qcom,cnss-peach@b0000000 {
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compatible = "qcom,cnss-peach";
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reg = <0x0 0xb0000000 0x0 0x10000>;
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reg-names = "smmu_iova_ipa";
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qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
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supported-ids = <0x110E>;
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wlan-en-gpio = <&tlmm 16 0>;
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qcom,bt-en-gpio = <&pmh0104_gpios 5 0>;
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qcom,sw-ctrl-gpio = <&tlmm 18 0>;
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wlan-host-sol-gpio = <&tlmm 204 0>;
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wlan-dev-sol-gpio = <&tlmm 205 0>;
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/* List of GPIOs to be setup for interrupt wakeup capable */
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mpm_wake_set_gpios = <18 19>;
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pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
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"sw_ctrl_wl_cx", "sol_default";
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pinctrl-0 = <&cnss_wlan_en_active>;
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pinctrl-1 = <&cnss_wlan_en_sleep>;
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pinctrl-2 = <&cnss_wlan_sw_ctrl>;
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pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
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pinctrl-4 = <&cnss_host_sol_default>;
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qcom,wlan;
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qcom,wlan-rc-num = <0>;
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qcom,wlan-ramdump-dynamic = <0x780000>;
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cnss-enable-self-recovery;
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qcom,wlan-cbc-enabled;
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use-pm-domain;
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qcom,same-dt-multi-dev;
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/* For AOP communication, use direct QMP instead of mailbox */
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qcom,qmp = <&aoss_qmp>;
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msix-match-addr = <0x3000>;
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vdd-wlan-aon-supply = <&L2G>;
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qcom,vdd-wlan-aon-config = <1800000 1800000 30000 0 1>;
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vdd-wlan-io12-supply = <&L3G>;
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qcom,vdd-wlan-io12-config = <1200000 1200000 30000 0 1>;
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vdd-wlan-cx-supply = <&S1J>;
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qcom,vdd-wlan-cx-config = <892000 1000000 0 0 1>;
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vdd-wlan-dig-supply = <&S2J>;
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qcom,vdd-wlan-dig-config = <892000 1000000 0 0 1>;
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vdd-wlan-rfa1-supply = <&S8F>;
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qcom,vdd-wlan-rfa1-config = <1876000 2000000 0 0 1>;
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vdd-wlan-rfa2-supply = <&S7F>;
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qcom,vdd-wlan-rfa2-config = <1328000 1340000 0 0 1>;
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vdd-wlan-ant-share-supply = <&L3K>;
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qcom,vdd-wlan-ant-share-config = <1200000 1200000 0 0 1>;
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qcom,vreg_pdc_map =
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"s1j", "bb",
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"s2j", "rf",
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"s7f", "rf",
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"s8f", "rf";
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qcom,pmu_vreg_map =
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"VDD_PMU_AON_I", "s2j",
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"VDD09_PMU_RFA_I", "s2j",
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"VDD19_PMU_RFA_I", "s8f",
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"VDD13_PMU_RFA_I", "s7f",
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"VDD095_MX_PMU", "s2j",
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"VDD095_PMU_CX", "s1j",
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"VDD095_PMU_BTCX", "s2j",
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"VDD095_PMU_BTMX", "s2j",
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"VDD13_PMU_PCIE_I", "s7f",
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"VDD13_PMU_PCIE12_I", "s7f";
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/* cpu mask used for wlan tx rx interrupt affinity
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* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
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*/
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wlan-txrx-intr-cpumask = <0x3 0x30>;
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};
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wlan_direct_link: qcom,cnss-direct-link {
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compatible = "qcom,cnss-direct-link";
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iommus = <&apps_smmu 0x100f 0x0>;
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qcom,iommu-group = <&cnss_audio_iommu_group0>;
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memory-region = <&direct_link_iommu_region_partition>;
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dma-coherent;
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direct_link_iommu_region_partition: direct_link_iommu_region_partition {
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iommu-addresses = <&wlan_direct_link 0x0 0x0 0x0 0x18000000>,
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<&wlan_direct_link 0x0 0xb0000000 0x0 0x50000000>;
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};
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};
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};
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&pcie_rp {
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cnss_pci0: cnss_pci0 {
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reg = <0 0 0 0 0>;
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qcom,iommu-group = <&cnss_audio_iommu_group0>;
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memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
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cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
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/* address-cells =3 size-cells=2 from canoe-pcie.dtsi */
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iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x18000000>,
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<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
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};
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};
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};
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