e6235a7c09
Enforce dependency of dma heap driver on SCM driver without which it will not work and this is in the preparation of adding interconnect voting in SCM node which if it gets added without this change dma heap driver can result in NULL pointer issue. Change-Id: I654e69398643b2e78d180c7167b29b62e7914f77 Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
354 lines
8.3 KiB
Plaintext
354 lines
8.3 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
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interrupt-parent = <&vgic>;
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chosen {
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bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable";
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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CPU0: cpu@0 {
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN
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&CLUSTER_PWR_DWN>;
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};
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CPU1: cpu@100 {
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN
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&CLUSTER_PWR_DWN>;
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};
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};
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idle-states {
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CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <550>;
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exit-latency-us = <1050>;
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min-residency-us = <7951>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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status = "disabled";
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};
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CLUSTER_PWR_DWN: d4 { /* C4+D4 */
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compatible = "arm,idle-state";
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idle-state-name = "l3-pc";
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entry-latency-us = <750>;
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exit-latency-us = <2350>;
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min-residency-us = <9144>;
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arm,psci-suspend-param = <0x40000044>;
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local-timer-stop;
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status = "disabled";
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};
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};
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qcom,vm-config {
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compatible = "qcom,vm-1.0";
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vm-type = "aarch64-guest";
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boot-config = "fdt,unified";
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os-type = "linux";
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kernel-entry-segment = "kernel";
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kernel-entry-offset = <0x0 0x0>;
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vendor = "QTI";
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image-name = "qcom,trustedvm";
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qcom,pasid = <0x0 0x1c>;
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qcom,qtee-config-info = "p=3,9,39,77,78,7C,8F,97,C8,FE,11B,159,199,47E,7F1,CDF;";
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qcom,secdomain-ids = <45>;
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qcom,primary-vm-index = <0>;
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vm-uri = "vmuid/trusted-ui";
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vm-guid = "598085da-c516-5b25-a9c1-927a02819770";
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qcom,sensitive;
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iomemory-ranges = <0x0 0x409000 0x0 0x409000 0x0 0x1000 0x0
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0x0 0xa20000 0x0 0xa20000 0x0 0x4000 0x0
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0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
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0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
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0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
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0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1
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0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1
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0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;
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/* For LEVM pored usecases is SE4 and SE7, for SE4 we used gpii4
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* and irq no is 315, for SE7 we used gpii5 and irq no is 316.
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*/
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gic-irq-ranges = <101 101
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315 315
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316 316>; /* PVM->SVM IRQ transfer */
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vm-attrs = "crash-fatal", "context-dump";
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memory {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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/*
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* IPA address linux image is loaded at. Must be within
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* first 1GB due to memory hotplug requirement.
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*/
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base-address = <0x0 0x28800000 >;
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};
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segments {
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config_cpio = <2>;
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};
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vcpus {
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config = "/cpus";
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affinity = "proxy";
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affinity-map = <0x5 0x6>;
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sched-priority = <0>; /* relative to PVM */
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sched-timeslice = <2000>; /* in ms */
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};
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interrupts {
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config = &vgic;
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};
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vdevices {
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generate = "/hypervisor";
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rm-rpc {
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vdevice-type = "rm-rpc";
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generate = "/hypervisor/qcom,resource-mgr";
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console-dev;
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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qcom,label = <0x1>;
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};
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virtio-mmio@0 {
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vdevice-type = "virtio-mmio";
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generate = "/virtio-mmio";
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peer-default;
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vqs-num = <0x1>;
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push-compatible = "virtio,mmio";
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dma-coherent;
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dma_base = <0x0 0x0>;
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memory {
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qcom,label = <0x11>; //for persist.img
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#address-cells = <0x2>;
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base = <0x0 0xDA6F8000>;
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};
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};
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virtio-mmio@1 {
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vdevice-type = "virtio-mmio";
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generate = "/virtio-mmio";
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peer-default;
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vqs-num = <0x2>;
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push-compatible = "virtio,mmio";
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dma-coherent;
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dma_base = <0x0 0x4000>;
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memory {
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qcom,label = <0x10>; //for system.img
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#address-cells = <0x2>;
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base = <0x0 0xDA6FC000>;
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};
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};
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swiotlb-shm {
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vdevice-type = "shm";
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generate = "/swiotlb";
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push-compatible = "swiotlb";
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peer-default;
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dma_base = <0x0 0x8000>;
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memory {
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qcom,label = <0x12>;
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#address-cells = <0x2>;
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base = <0x0 0xDA700000>;
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};
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};
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mem-buf-message-queue-pair {
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vdevice-type = "message-queue-pair";
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generate = "/hypervisor/membuf-msgq-pair";
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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peer-default;
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qcom,label = <0x0000001>;
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};
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gpiomem0 {
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vdevice-type = "iomem";
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patch = "/soc/tlmm-vm-mem-access";
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push-compatible = "qcom,tlmm-vm-mem-access";
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peer-default;
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memory {
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qcom,label = <0x8>;
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qcom,mem-info-tag = <0x3>;
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allocate-base;
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};
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};
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test-dbl-tuivm {
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vdevice-type = "doorbell";
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generate = "/hypervisor/test-dbl-tuivm";
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qcom,label = <0x4>;
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peer-default;
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};
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test-dbl-tuivm-source {
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vdevice-type = "doorbell-source";
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generate = "/hypervisor/test-dbl-tuivm-source";
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qcom,label = <0x4>;
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peer-default;
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};
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test-msgq-tuivm {
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vdevice-type = "message-queue-pair";
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generate = "/hypervisor/test-msgq-tuivm-pair";
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message-size = <0xf0>;
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queue-depth = <0x8>;
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qcom,label = <0x4>;
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peer-default;
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};
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vcpu-sched-test-msgq {
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vdevice-type = "message-queue-pair";
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generate = "/hypervisor/sched-test-msgq-pair";
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message-size = <0xf0>;
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queue-depth = <0x8>;
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qcom,label = <0x8>;
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peer-default;
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};
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};
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};
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firmware: firmware {
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qcom_scm: qcom_scm {
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compatible = "qcom,scm";
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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vm_tlmm_irq: vm-tlmm-irq@0 {
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compatible = "qcom,tlmm-vm-irq";
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reg = <0x0 0x0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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tlmm: pinctrl@f000000 {
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compatible = "qcom,pineapple-vm-pinctrl";
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reg = <0x0F000000 0x1000000>;
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interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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/* Valid pins */
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gpios = /bits/ 16 <86 87 133 137 48 49 50 51 161 162 91 60 61 62 63 88>;
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};
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tlmm-vm-mem-access {
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compatible = "qcom,tlmm-vm-mem-access";
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tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 133 0 &tlmm 137 0 &tlmm 48 0
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&tlmm 49 0 &tlmm 50 0 &tlmm 51 0 &tlmm 161 0 &tlmm 162 0
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&tlmm 91 0 &tlmm 60 0 &tlmm 61 0 &tlmm 62 0 &tlmm 63 0
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&tlmm 88 0>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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vgic: interrupt-controller@17100000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x17100000 0x10000>, /* GICD */
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<0x17180000 0x100000>; /* GICR * 8 */
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};
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ipcc_mproc_ns1: qcom,ipcc@409000 {
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compatible = "qcom,ipcc";
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reg = <0x409000 0x1000>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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always-on;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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qcom,mem-buf {
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compatible = "qcom,mem-buf";
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qcom,mem-buf-capabilities = "consumer";
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qcom,vmid = <45>;
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};
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qcom,mem-buf-msgq {
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compatible = "qcom,mem-buf-msgq";
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};
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virtio_mem_device {
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compatible = "qcom,virtio-mem";
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/* Must be memory_block_size_bytes() aligned */
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qcom,max-size = <0x0 0x10000000>;
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qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
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qcom,block-size = <0x400000>;
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};
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qcom,test-dbl-tuivm {
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compatible = "qcom,gh-dbl";
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qcom,label = <0x4>;
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};
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qcom,test-msgq-tuivm {
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compatible = "qcom,gh-msgq-test";
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gunyah-label = <4>;
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affinity = <0>;
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};
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qcom,gh-qtimer@17425000 {
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compatible = "qcom,gh-qtmr";
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reg = <0x17425000 0x1000>;
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reg-names = "qtmr-base";
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "qcom,qtmr-intr";
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qcom,secondary;
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};
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};
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#include "msm-arm-smmu-pineapple-vm.dtsi"
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#include "pineapple-vm-dma-heaps.dtsi"
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