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cd38f518ce515e7ad3a7d65b8e998bddbe7d5a78
android_kernel_samsung_sm87…/qcom/monaco.dtsi
Saranya R 6833986c6f ARM: dts: msm: Add support for debug info for monaco 
Reserve debug info region of 4KB for monaco.

Change-Id: I9481c9862838cd754a063a351dd02578d2b3dd2f
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
2025-04-14 03:00:49 -07:00

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,dispcc-monaco.h>
#include <dt-bindings/clock/qcom,gcc-monaco.h>
#include <dt-bindings/clock/qcom,gpucc-monaco.h>
#include <dt-bindings/soc/qcom,dcc_v2.h>
#include <dt-bindings/interconnect/qcom,monaco.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/spmi/spmi.h>
/ {
model = "Qualcomm Technologies, Inc. Monaco";
compatible = "qcom,monaco";
qcom,msm-id = <486 0x10000>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
aliases {
mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
sdhc2 = &sdhc_3; /*SDC3 SDIO slot*/
serial0 = &qupv3_se6_2uart;
hsuart0 = &qupv3_se5_4uart;
i2c1 = &qupv3_se1_i2c;
};
firmware: firmware {};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
cpu-idle-states = <&SILVER_OFF>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
enable-method = "psci";
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
cache-size = <0x80000>;
cache-level = <2>;
};
L1_I_0: l1-icache {
compatible = "cache";
};
L1_D_0: l1-dcache {
compatible = "cache";
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
cpu-idle-states = <&SILVER_OFF>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
enable-method = "psci";
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L1_I_1: l1-icache {
compatible = "cache";
};
L1_D_1: l1-dcache {
compatible = "cache";
};
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
cpu-idle-states = <&SILVER_OFF>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
enable-method = "psci";
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L1_I_2: l1-icache {
compatible = "cache";
};
L1_D_2: l1-dcache {
compatible = "cache";
};
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
cpu-idle-states = <&SILVER_OFF>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
enable-method = "psci";
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L1_I_3: l1-icache {
compatible = "cache";
};
L1_D_3: l1-dcache {
compatible = "cache";
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
};
};
idle-states {
SILVER_OFF: silver-c3 { /* C3 */
compatible = "arm,idle-state";
idle-state-name = "pc";
entry-latency-us = <297>;
exit-latency-us = <324>;
min-residency-us = <1110>;
arm,psci-suspend-param = <0x40000003>;
local-timer-stop;
};
SILVER_CLUSTER_D3: silver-cluster-d3 { /* D3 */
compatible = "domain-idle-state";
idle-state-name = "pwr-l2-pc";
entry-latency-us = <800>;
exit-latency-us = <2118>;
min-residency-us = <7376>;
arm,psci-suspend-param = <0x41000043>;
};
};
soc: soc { };
chosen {
bootargs = "loglevel=6 log_buf_len=256K kpti=off kernel.panic_on_rcu_stall=1 msm_rtb.filter=0x237 rcupdate.rcu_expedited=1 rcu_nocbs=0-3 ftrace_dump_on_oops fw_devlink.strict=1 printk.console_no_auto_verbose=1 irqaffinity=0-2 cpufreq.default_governor=performance slub_debug=- randomize_kstack_offset=on ";
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
oda_region: oda_region@45700000 {
no-map;
reg = <0x0 0x45700000 0x0 0x300000>;
};
deepsleep_region: deepsleep_region@45A00000 {
no-map;
reg = <0x0 0x45A00000 0x0 0x100000>;
};
hyp_region: hyp_region@45B00000 {
no-map;
reg = <0x0 0x45B00000 0x0 0x300000>;
};
xbl_aop_mem: xbl_aop_mem@45e00000 {
no-map;
reg = <0x0 0x45e00000 0x0 0x11B000>;
};
sec_apps_mem: sec_apps_region@45fff000 {
no-map;
reg = <0x0 0x45fff000 0x0 0x1000>;
};
smem_region: smem@46000000 {
no-map;
reg = <0x0 0x46000000 0x0 0x200000>;
};
wlan_msa_mem: wlan_msa_region@46200000 {
no-map;
reg = <0x0 0x46200000 0x0 0x100000>;
};
pil_modem_mem: modem_region@4ab00000 {
no-map;
reg = <0x0 0x4ab00000 0x0 0x5E00000>;
};
video_mem: video_region@50900000 {
no-map;
reg = <0x0 0x50900000 0x0 0x700000>;
};
pil_adsp_mem: adsp_regions@51000000 {
no-map;
reg = <0x0 0x51000000 0x0 0x1900000>;
};
pil_ipa_fw_mem: ips_fw_region@52900000 {
no-map;
reg = <0x0 0x52900000 0x0 0x10000>;
};
pil_ipa_gsi_mem: ipa_gsi_region@52910000 {
no-map;
reg = <0x0 0x52910000 0x0 0x5000>;
};
pil_gpu_mem: gpu_region@52915000 {
no-map;
reg = <0x0 0x52915000 0x0 0x2000>;
};
stats_region: stats_region@60000000 {
no-map;
reg = <0x0 0x60000000 0x0 0x100000>;
};
removed_region: removed_region@60100000 {
no-map;
reg = <0x0 0x60100000 0x0 0x1E00000>;
};
dump_mem: mem_dump_region {
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
size = <0 0x800000>;
};
user_contig_mem: user_contig_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
secure_display_memory: secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x5c00000>;
status = "disabled";
};
non_secure_display_memory: non_secure_display_region {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
size = <0x0 0xa400000>;
alignment = <0x0 0x400000>;
};
splash_memory: splash_region@5c000000 {
reg = <0x0 0x5c000000 0x0 0x00f00000>;
label = "cont_splash_region";
};
dfps_data_memory: dfps_data_region@5cf00000 {
reg = <0x0 0x5cf00000 0x0 0x0100000>;
label = "dfps_data_region";
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x800000>;
};
/* global autoconfigured region for contiguous allocations */
system_cma: linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
linux,cma-default;
};
kinfo_mem: debug_kinfo_region {
alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
size = <0x0 0x1000>;
no-map;
};
};
};
&firmware {
qcom_scm: scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
#gpio-cells = <2>;
compatible = "simple-bus";
intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0xf200000 0x10000>, /* GICD */
<0xf300000 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: cpu-pd0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD1: cpu-pd1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD2: cpu-pd2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD3: cpu-pd3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CLUSTER_PD: cluster-pd0 {
#power-domain-cells = <0>;
domain-idle-states = <&SILVER_CLUSTER_D3>;
};
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
qcom,mem-buf {
compatible = "qcom,mem-buf";
qcom,mem-buf-capabilities = "supplier";
qcom,vmid = <3>;
};
memtimer: timer@f120000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x0f120000 0x1000>;
clock-frequency = <19200000>;
frame@f121000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0f121000 0x1000>,
<0x0f122000 0x1000>;
};
frame@f123000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf123000 0x1000>;
status = "disabled";
};
frame@f124000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf124000 0x1000>;
status = "disabled";
};
frame@f125000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf125000 0x1000>;
status = "disabled";
};
frame@f126000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf126000 0x1000>;
status = "disabled";
};
frame@f127000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf127000 0x1000>;
status = "disabled";
};
frame@f128000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf128000 0x1000>;
status = "disabled";
};
};
cpu_pmu: cpu-pmu {
compatible = "arm,armv8-pmuv3";
qcom,irq-is-percpu;
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
};
qcom,msm-imem@c125000 {
compatible = "qcom,msm-imem";
reg = <0xc125000 0x1000>;
ranges = <0x0 0xc125000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
pil@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;
};
pil@6dc {
compatible = "qcom,msm-imem-pil-disable-timeout";
reg = <0x6dc 0x4>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
google,debug-kinfo {
compatible = "google,debug-kinfo";
memory-region = <&kinfo_mem>;
};
mini_dump_mode {
compatible = "qcom,minidump";
status = "ok";
};
vendor_hooks: qcom,cpu-vendor-hooks {
compatible = "qcom,cpu-vendor-hooks";
};
logbuf: qcom,logbuf-vendor-hooks {
compatible = "qcom,logbuf-vendor-hooks";
};
qcom,mpm2-slepp-counter@4403000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0x4403000 0x1000>;
clock-frequency = <32768>;
};
qcom,rmtfs_sharedmem@0 {
compatible = "qcom,sharedmem-uio";
reg = <0x0 0x280000>;
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
qcom,guard-memory;
qcom,vm-nav-path;
};
qcom,chd_silver {
compatible = "qcom,core-hang-detect";
label = "silver";
qcom,chd-percpu-info = <&CPU0 0x0f1880b0 0x0f1880b8>,
<&CPU1 0x0f1980b0 0x0f1980b8>,
<&CPU2 0x0f1a80b0 0x0f1a80b8>,
<&CPU3 0x0f1b80b0 0x0f1b80b8>;
};
qcom_qseecom: qseecom@61800000 {
compatible = "qcom,qseecom";
reg = <0x61800000 0x2100000>;
reg-names = "secapp-region";
memory-region = <&qseecom_mem>;
qseecom_mem = <&qseecom_mem>;
qseecom_ta_mem = <&qseecom_ta_mem>;
user_contig_mem = <&user_contig_mem>;
qcom,hlos-num-ce-hw-instances = <1>;
qcom,hlos-ce-hw-instance = <0>;
qcom,qsee-ce-hw-instance = <0>;
qcom,disk-encrypt-pipe-pair = <2>;
qcom,support-fde;
qcom,fde-key-size;
qcom,appsbl-qseecom-support;
qcom,commonlib64-loaded-by-uefi;
interconnect-names = "data_path";
interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
clock-names =
"core_clk_src", "core_clk",
"iface_clk", "bus_clk";
clocks =
<&rpmcc RPM_SMD_CE1_CLK>,
<&rpmcc RPM_SMD_CE1_CLK>,
<&rpmcc RPM_SMD_CE1_CLK>,
<&rpmcc RPM_SMD_CE1_CLK>;
qcom,ce-opp-freq = <192000000>;
qcom,qsee-reentrancy-support = <2>;
};
qtee_shmbridge {
compatible = "qcom,tee-shared-memory-bridge";
};
qcom_smcinvoke: smcinvoke@61800000 {
compatible = "qcom,smcinvoke";
};
qcom_hwkm: hwkm@4440000 {
compatible = "qcom,hwkm";
reg = <0x4440000 0x9000>;
reg-names = "km_master";
qcom,enable-hwkm-clk;
clock-names = "km_clk_src";
clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
qcom,op-freq-hz = <75000000>;
};
qcom_tzlog: tz-log@c125720 {
compatible = "qcom,tz-log";
reg = <0xc125720 0x3000>;
qcom,hyplog-enabled;
hyplog-address-offset = <0x410>;
hyplog-size-offset = <0x414>;
};
qcom_rng: qrng@4453000 {
compatible = "qcom,msm-rng";
reg = <0x4453000 0x1000>;
qcom,no-qrng-config;
interconnect-names = "data_path";
interconnects = <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_HWKM>;
clock-names = "km_clk_src";
clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
};
qcom_cedev: qcedev@1b20000 {
compatible = "qcom,qcedev";
reg = <0x1b20000 0x20000>,
<0x1b04000 0x24000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
qcom,bam-pipe-pair = <3>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,bam-ee = <0>;
clock-names =
"core_clk_src", "core_clk",
"iface_clk", "bus_clk";
clocks =
<&rpmcc RPM_SMD_CE1_CLK>,
<&rpmcc RPM_SMD_CE1_CLK>,
<&rpmcc RPM_SMD_CE1_CLK>,
<&rpmcc RPM_SMD_CE1_CLK>;
qcom,ce-opp-freq = <192000000>;
qcom,smmu-s1-enable;
interconnect-names = "data_path";
interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
iommus = <&apps_smmu 0x0086 0x0011>,
<&apps_smmu 0x0096 0x0011>;
qcom,iommu-dma = "atomic";
qcom_cedev_ns_cb {
compatible = "qcom,qcedev,context-bank";
label = "ns_context";
iommus = <&apps_smmu 0x92 0>,
<&apps_smmu 0x98 0x1>,
<&apps_smmu 0x9F 0>;
qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
};
qcom_cedev_s_cb {
compatible = "qcom,qcedev,context-bank";
label = "secure_context";
iommus = <&apps_smmu 0x93 0>,
<&apps_smmu 0x9C 0x1>,
<&apps_smmu 0x9E 0>;
qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
qcom,secure-context-bank;
};
};
wdog: qcom,wdt@f017000 {
compatible = "qcom,msm-watchdog";
reg = <0xf017000 0x1000>;
reg-names = "wdt-base";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
qcom,bark-time = <11000>;
qcom,pet-time = <9360>;
qcom,ipi-ping;
qcom,wakeup-enable;
};
eud: qcom,msm-eud@1610000 {
compatible = "qcom,msm-eud";
interrupt-names = "eud_irq";
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x1610000 0x2000>,
<0x1612000 0x1000>,
<0x3E5018 0x4>;
reg-names = "eud_base", "eud_mode_mgr2",
"eud_tcsr_check_reg";
qcom,secure-eud-en;
qcom,eud-tcsr-check-enable;
qcom,eud-clock-vote-req;
clocks = <&gcc GCC_AHB2PHY_USB_CLK>;
clock-names = "eud_ahb2phy_clk";
status = "ok";
};
qcom,sps {
compatible = "qcom,msm-sps-4k";
qcom,pipe-attr-ee;
};
qfprom: qfprom@1b40000 {
compatible = "qcom,qfprom";
reg = <0x1b40000 0x7000>;
#address-cells = <1>;
#size-cells = <1>;
read-only;
ranges;
adsp_variant: adsp_variant@6011 {
reg = <0x6011 0x1>;
bits = <3 1>;
};
};
mem_dump {
compatible = "qcom,mem-dump";
memory-region = <&dump_mem>;
static_dump {
qcom,static-mem-dump;
c0_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x0>;
};
c1_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x1>;
};
c2_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x2>;
};
c3_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x3>;
};
l1_icache0 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x60>;
};
l1_icache1 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x61>;
};
l1_icache2 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x62>;
};
l1_icache3 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x63>;
};
l1_dcache0 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x80>;
};
l1_dcache1 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x81>;
};
l1_dcache2 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x82>;
};
l1_dcache3 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x83>;
};
l2_tlb0 {
qcom,dump-size = <0x2000>;
qcom,dump-id = <0x120>;
};
l2_tlb1 {
qcom,dump-size = <0x2000>;
qcom,dump-id = <0x121>;
};
l2_tlb2 {
qcom,dump-size = <0x2000>;
qcom,dump-id = <0x122>;
};
l2_tlb3 {
qcom,dump-size = <0x2000>;
qcom,dump-id = <0x123>;
};
pmic {
qcom,dump-size = <0x200000>;
qcom,dump-id = <0xe4>;
};
tmc_etf {
qcom,dump-size = <0x8000>;
qcom,dump-id = <0xf0>;
};
etr_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x100>;
};
etf_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x101>;
};
};
};
qcom,smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
/* ipa - inbound entry from mss */
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
qcom,entry-name = "rdbg";
#qcom,smem-state-cells = <1>;
};
smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
qcom,entry-name = "rdbg";
interrupt-controller;
#interrupt-cells = <2>;
};
sleepstate_smp2p_out_sensor: sleepstate-out-sensor {
qcom,entry-name = "sleepstate";
#qcom,smem-state-cells = <1>;
};
sleepstate_smp2p_in_sensor: qcom,sleepstate-in-sensor {
qcom,entry-name = "sleepstate_see";
interrupt-controller;
#interrupt-cells = <2>;
};
sleepstate_smp2p_out_ult: sleepstate-out-ult {
qcom,entry-name = "sleepstate_ult";
#qcom,smem-state-cells = <1>;
};
sleepstate_smp2p_in_ult: qcom,sleepstate-in-ult {
qcom,entry-name = "sleepstate_ult_in";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p_sleepstate_sensor {
compatible = "qcom,smp2p-sleepstate";
qcom,smem-states = <&sleepstate_smp2p_out_sensor 0>;
interrupt-parent = <&sleepstate_smp2p_in_sensor>;
interrupts = <0 0>;
interrupt-names = "smp2p-sleepstate-in";
};
qcom,smp2p_sleepstate_ult {
compatible = "qcom,smp2p-sleepstate";
qcom,smem-states = <&sleepstate_smp2p_out_ult 0>;
interrupt-parent = <&sleepstate_smp2p_in_ult>;
interrupts = <0 0>;
interrupt-names = "smp2p-sleepstate-in";
};
adsp_pas:remoteproc-adsp@ab00000 {
compatible = "qcom,monaco-adsp-pas";
reg = <0xab00000 0x00100>;
vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>;
reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>;
vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "xo";
memory-region = <&pil_adsp_mem>;
/* Inputs from lpass */
interrupts-extended = <&intc 0 282 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 0>,
<&adsp_smp2p_in 2 0>,
<&adsp_smp2p_in 1 0>,
<&adsp_smp2p_in 3 0>,
<&adsp_smp2p_in 7 0>,
<&adsp_smp2p_in 9 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack",
"shutdown-ack",
"dsentry-ack";
/* Outputs to lpass */
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink_edge: glink-edge {
qcom,remote-pid = <2>;
transport = "smem";
mboxes = <&apcs_glb 8>;
mbox-names = "adsp_smem";
interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
label = "adsp";
qcom,glink-label = "lpass";
qcom,adsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
qcom,non-wake-svc = <0x51
0x190>;
};
};
};
modem_pas: remoteproc-mss@6080000 {
compatible = "qcom,monaco-modem-pas";
reg = <0x6080000 0x100>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "xo";
cx-supply = <&VDD_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
reg-names = "cx";
memory-region = <&pil_modem_mem>;
/* Inputs from mss */
interrupts-extended = <&intc 0 307 1>,
<&modem_smp2p_in 0 0>,
<&modem_smp2p_in 2 0>,
<&modem_smp2p_in 1 0>,
<&modem_smp2p_in 3 0>,
<&modem_smp2p_in 7 0>,
<&modem_smp2p_in 9 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack",
"shutdown-ack",
"dsentry-ack";
/* Outputs to mss */
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
qcom,remote-pid = <1>;
transport = "smem";
mboxes = <&apcs_glb 12>;
mbox-names = "mpss_smem";
interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,glink-label = "mpss";
qcom,modem_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,modem_ds {
qcom,glink-channels = "DS";
qcom,intents = <0x4000 2>;
};
};
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <38400000>;
clock-output-names = "xo_board";
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
};
rpmcc: qcom,rpmcc {
compatible = "qcom,rpmcc-monaco";
#clock-cells = <1>;
#reset-cells = <1>;
};
gcc: clock-controller@1410000 {
compatible = "qcom,monaco-gcc", "syscon";
reg = <0x1400000 0x1e0000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
dispcc: clock-controller@5f00000 {
compatible = "qcom,monaco-dispcc", "syscon";
reg = <0x05f00000 0x20000>;
reg-names = "cc_base";
clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main",
"sleep_clk";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<&gcc GPLL0>, <&sleep_clk>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
#clock-cells = <1>;
#reset-cells = <1>;
};
gpucc: clock-controller@5990000 {
compatible = "qcom,monaco-gpucc", "syscon";
reg = <0x5990000 0x9000>;
reg-names = "cc_base";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&gcc GPLL0>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main",
"gcc_gpu_snoc_dvm_gfx_clk";
vdd_cx-supply = <&VDD_CX_LEVEL>;
#clock-cells = <1>;
#reset-cells = <1>;
};
mccc_debug: syscon@447d200 {
compatible = "syscon";
reg = <0x0447d200 0x100>;
};
apsscc_debug: syscon@f11101c {
compatible = "syscon";
reg = <0xf11101c 0x4>;
};
debugcc: clock-controller@0 {
compatible = "qcom,monaco-debugcc";
qcom,gcc = <&gcc>;
qcom,dispcc = <&dispcc>;
qcom,gpucc = <&gpucc>;
qcom,mccc = <&mccc_debug>;
qcom,apsscc = <&apsscc_debug>;
clock-names = "xo_clk_src";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
#clock-cells = <1>;
};
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw";
reg = <0xf521000 0x1400>;
reg-names = "freq-domain0";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
qcom,no-accumulative-counter;
qcom,max-lut-entries = <12>;
#freq-domain-cells = <1>;
};
qcom,cpufreq-hw-debug@f521000 {
compatible = "qcom,cpufreq-hw-debug";
reg = <0xf521000 0x1400>;
reg-names = "domain-top";
qcom,freq-hw-domain = <&cpufreq_hw 0>;
};
spmi_bus: qcom,spmi@1c40000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x1c40000 0x1100>,
<0x1e00000 0x2000000>,
<0x3e00000 0x100000>,
<0x3f00000 0xa0000>,
<0x1c0a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,mid = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
thermal_zones: thermal-zones {};
tcsr_mutex_block: syscon@00340000 {
compatible = "syscon";
reg = <0x340000 0x20000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_block 0 0x1000>;
#hwlock-cells = <1>;
};
tcsr: syscon@03c0000 {
compatible = "syscon";
reg = <0x03c0000 0x30000>;
};
smem: qcom,smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
hwlocks = <&tcsr_mutex 3>;
};
rpm_msg_ram: memory@045f0000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x45f0000 0x4000>;
};
apcs_glb: mailbox@0f111000 {
compatible = "qcom,monaco-apcs-hmss-global";
reg = <0xF111000 0x1000>;
#mbox-cells = <1>;
};
qcom,msm-adsprpc-mem {
compatible = "qcom,msm-adsprpc-mem-region";
memory-region = <&adsp_mem>;
restrict-access;
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
};
qcom,glink {
compatible = "qcom,glink";
};
qcom,glinkpkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-at-mdm0 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DS";
qcom,glinkpkt-dev-name = "at_mdm0";
};
qcom,glinkpkt-apr-apps2 {
qcom,glinkpkt-edge = "adsp";
qcom,glinkpkt-ch-name = "apr_apps2";
qcom,glinkpkt-dev-name = "apr_apps2";
};
qcom,glinkpkt-data40-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA40_CNTL";
qcom,glinkpkt-dev-name = "smdcntl8";
};
qcom,glinkpkt-data1 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA1";
qcom,glinkpkt-dev-name = "smd7";
};
qcom,glinkpkt-data4 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA4";
qcom,glinkpkt-dev-name = "smd8";
};
qcom,glinkpkt-data11 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA11";
qcom,glinkpkt-dev-name = "smd11";
};
qcom,glinkpkt-slate-ssc-hal {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_hal";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_hal";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-sso-hal {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "sso_hal";
qcom,glinkpkt-dev-name = "glinkpkt_slate_sso_hal";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-cam-hal {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "cam_hal";
qcom,glinkpkt-dev-name = "glinkpkt_slate_cam_hal";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-display-ctrl {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "display-ctrl";
qcom,glinkpkt-dev-name = "glink_pkt_slate_display_ctrl";
};
qcom,glinkpkt-slate-location-ctrl {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "location_ctrl";
qcom,glinkpkt-dev-name = "glink_pkt_slate_location_ctrl";
};
qcom,glinkpkt-slate-display-data {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "display-data";
qcom,glinkpkt-dev-name = "glink_pkt_slate_display_data";
};
qcom,glinkpkt-slate-touch-ctrl {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "touch-ctrl";
qcom,glinkpkt-dev-name = "glink_pkt_slate_touch_ctrl";
};
qcom,glinkpkt-slate-ssc-usta {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_usta";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_usta";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-0 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_0";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_0";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-1 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_1";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_1";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-2 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_2";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_2";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-3 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_3";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_3";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-4 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_4";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_4";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-5 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_5";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_5";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-6 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_6";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_6";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-7 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_7";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_7";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-8 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_8";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_8";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-9 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_9";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_9";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-10 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_10";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_10";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-11 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_11";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_11";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-12 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_12";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_12";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-13 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_13";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_13";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-ssc-test-14 {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ssc_test_14";
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_test_14";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-slate-apps-diag-cntl {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "DIAG_SLATE_APPS_CNTL";
qcom,glinkpkt-dev-name = "slate_apps_cntl";
qcom,glinkpkt-fragmented-read;
};
qcom,glinkpkt-slate-apps-diag-cmd {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "DIAG_SLATE_APPS_CMD";
qcom,glinkpkt-dev-name = "slate_apps_cmd";
qcom,glinkpkt-fragmented-read;
};
qcom,glinkpkt-slate-apps-diag-data {
qcom,glinkpkt-edge = "lpass";
qcom,glinkpkt-ch-name = "DIAG_SLATE_APPS_DATA";
qcom,glinkpkt-dev-name = "slate_apps_data";
qcom,glinkpkt-fragmented-read;
};
qcom,glinkpkt-slate-adsp-diag-cntl {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "DIAG_SLATE_ADSP_CNTL";
qcom,glinkpkt-dev-name = "slate_adsp_cntl";
qcom,glinkpkt-fragmented-read;
};
qcom,glinkpkt-slate-adsp-diag-cmd {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "DIAG_SLATE_ADSP_CMD";
qcom,glinkpkt-dev-name = "slate_adsp_cmd";
qcom,glinkpkt-fragmented-read;
};
qcom,glinkpkt-slate-adsp-diag-data {
qcom,glinkpkt-edge = "lpass";
qcom,glinkpkt-ch-name = "DIAG_SLATE_ADSP_DATA";
qcom,glinkpkt-dev-name = "slate_adsp_data";
qcom,glinkpkt-fragmented-read;
};
qcom,glinkpkt-slate-tme-data {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "LOGPROXY_SLATE_TME_DATA";
qcom,glinkpkt-dev-name = "slate_tme_log";
qcom,glinkpkt-fragmented-read;
};
qcom,glinkpkt-haptics-offload-ctrl {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "slate-haptics-offload";
qcom,glinkpkt-dev-name = "glinkpkt_slate_haptics_offload";
};
qcom,glinkpkt-slate-ux-ctl {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "slate-ux-ctl";
qcom,glinkpkt-dev-name = "glink_pkt_slate_ux_ctl";
};
qcom,glinkpkt-slate-qcli {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "slate-qcli";
qcom,glinkpkt-dev-name = "glink_pkt_slate_qcli";
qcom,glinkpkt-fragmented-read;
};
qcom,glinkpkt-slate-bt-ctrl {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "slate_bt_ctrl";
qcom,glinkpkt-dev-name = "glink_pkt_slate_bt_ctrl";
};
qcom,glinkpkt-bt-offload-event {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "bt_offload_event";
qcom,glinkpkt-dev-name = "glink_pkt_bt_offload_event";
};
qcom,glinkpkt-bt-app-offload-data {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "slate_bt_app";
qcom,glinkpkt-dev-name = "glink_pkt_slate_bt_app";
};
qcom,glinkpkt-slate-dfu {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "slate-dfu";
qcom,glinkpkt-dev-name = "glink_pkt_slate_dfu";
};
qcom,glinkpkt-slate-custom-data {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "slate_custom_data";
qcom,glinkpkt-dev-name = "glink_pkt_slate_custom_data";
};
qcom,glinkpkt-ss-bt-ctrl {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ss_bt_ctrl";
qcom,glinkpkt-dev-name = "glink_pkt_ss_bt_ctrl";
};
qcom,glinkpkt-ss-bt-data {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ss_bt_data";
qcom,glinkpkt-dev-name = "glink_pkt_ss_bt_data";
};
qcom,glinkpkt-ss-bt-le-data {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ss_bt_le_data";
qcom,glinkpkt-dev-name = "glink_pkt_ss_bt_le_data";
};
qcom,glinkpkt-ss-bt-ssr-data {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ss_bt_ssr_data";
qcom,glinkpkt-dev-name = "glink_pkt_ss_bt_ssr_data";
};
qcom,glinkpkt-ss-bt-obex-data {
qcom,glinkpkt-edge = "slate";
qcom,glinkpkt-ch-name = "ss_bt_obex_data";
qcom,glinkpkt-dev-name = "glink_pkt_ss_bt_obex_data";
};
};
dcc: dcc_v2@16FF000 {
compatible = "qcom,dcc-v2";
reg = <0x16FF000 0x1000>,
<0x1681000 0x2000>;
qcom,transaction_timeout = <0>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x1000>;
per-ll-reg-cnt = <7>;
ll-reg-offsets = <0x02C 0x034 0x038 0x03C 0x044 0x048 0x030 0x0AC
0x0B4 0x0B8 0x0BC 0x0C4 0x0C8 0x0B0 0x12C 0x134
0x138 0x13C 0x144 0x148 0x130 0x1AC 0x1B4 0x1B8
0x1BC 0x1C4 0x1C8 0x1B0>;
};
clk_virt: interconnect {
compatible = "qcom,monaco-clk_virt";
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_QUP_CLK>,
<&rpmcc RPM_SMD_QUP_A_CLK>;
};
mmnrt_virt: interconnect@0 {
compatible = "qcom,monaco-mmnrt_virt";
#interconnect-cells = <1>;
qcom,util-factor = <142>;
qcom,keepalive;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_MMNRT_CLK>,
<&rpmcc RPM_SMD_MMNRT_A_CLK>;
};
mmrt_virt: interconnect@1 {
compatible = "qcom,monaco-mmrt_virt";
#interconnect-cells = <1>;
qcom,util-factor = <142>;
qcom,keepalive;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_MMRT_CLK>,
<&rpmcc RPM_SMD_MMRT_A_CLK>;
};
system_noc: interconnect@1880000 {
reg = <0x01880000 0x5e200>;
compatible = "qcom,monaco-system_noc";
#interconnect-cells = <1>;
qcom,keepalive;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>,
<&rpmcc RPM_SMD_IPA_CLK>,
<&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
<&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>;
};
config_noc: interconnect@1900000 {
reg = <0x01900000 0x1000>;
compatible = "qcom,monaco-config_noc";
#interconnect-cells = <1>;
qcom,keepalive;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
<&rpmcc RPM_SMD_CNOC_A_CLK>;
};
bimc: interconnect@4480000 {
reg = <0x04480000 0x80000>;
compatible = "qcom,monaco-bimc";
#interconnect-cells = <1>;
qcom,util-factor = <151>;
qcom,keepalive;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};
rpm_bus: qcom,rpm-smd {
compatible = "qcom,rpm-smd";
rpm-channel-name = "rpm_requests";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
rpm-channel-type = <15>; /* SMD_APPS_RPM */
power-domains = <&CLUSTER_PD>;
};
cluster-device {
compatible = "qcom,lpm-cluster-dev";
power-domains = <&CLUSTER_PD>;
};
rpm-sleep-stats@4690000 {
compatible = "qcom,rpm-stats-v2";
reg = <0x04690000 0x400>;
ss-name = "modem", "adsp", "adsp_island", "cdsp", "apss";
};
sdhc1_opp_table: sdhc1-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-peak-kBps = <500000 200000>;
opp-avg-kBps = <104000 0>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
opp-peak-kBps = <2500000 1000000>;
opp-avg-kBps = <400000 0>;
};
};
sdhc_1: sdhci@4744000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x04744000 0x1000>, <0x04745000 0x1000>,
<0x04748000 0x18000>;
reg-names = "hc", "cqhci", "ice";
iommus = <&apps_smmu 0xC0 0x0>;
qcom,iommu-dma = "bypass";
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,ice-use-hwkm;
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "core", "iface", "ice_core";
qcom,ice-clk-rates = <300000000 100000000>;
interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
operating-points-v2 = <&sdhc1_opp_table>;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x000F642C 0x0 0x01 0x2c010800 0x80040868>;
qcom,restore-after-cx-collapse;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
no-sd;
no-sdio;
bus-width = <8>;
non-removable;
supports-cqe;
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
cap-mmc-hw-reset;
mmc-rst-n-disable;
/* Add dt entry for gcc hw reset */
resets = <&gcc GCC_SDCC1_BCR>;
reset-names = "core_reset";
status = "disabled";
qos0 {
mask = <0x0f>;
vote = <43>;
};
};
sdhc_3: sdhci@4784000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x04784000 0x1000>;
reg-names = "hc_mem";
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
qcom,msm-bus,name = "sdhc3";
qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
/* No Vote */
<0 0>, <0 0>,
/* 400 KB/s*/
<1046 3200>, <1600 1600>,
/* 25 MB/s */
<65360 250000>, <100000 133320>,
/* 50 MB/s */
<130718 250000>, <133320 133320>,
/* 100 MB/s */
<261438 250000>, <150000 133320>,
/* 200 MB/s */
<261438 800000>, <300000 300000>,
/* Max. bandwidth */
<1338562 4096000>, <1338562 4096000>;
qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
100000000 200000000 4294967295>;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>;
bus-width = <4>;
iommus = <&apps_smmu 0xA0 0x0>;
qcom,iommu-dma = "bypass";
qcom,devfreq,freq-table = <400000 20000000 25000000 50000000>;
status = "disabled";
};
mpm: interrupt-controller@45f01b8 {
compatible = "qcom,mpm-monaco", "qcom,mpm";
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
reg = <0x45f01b8 0x1000>,
<0xf111008 0x4>,
<0xf121000 0x1000>;
reg-names = "vmpm", "ipc", "timer";
qcom,num-mpm-irqs = <96>;
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <2>;
};
qcom-secure-buffer {
compatible = "qcom,secure-buffer";
};
qcom,power-state {
/* compatible = "qcom,power-state"; */
qcom,subsys-name = "lpass", "mpss";
qcom,rproc-handle = <&adsp_pas>, <&modem_pas>;
};
slimbam: bamdma@A584000 {
compatible = "qcom,bam-v1.7.0";
qcom,controlled-remotely;
reg = <0xA584000 0x20000>, <0xA66F000 0x1000>;
reg-names = "bam", "bam_remote_mem";
num-channels = <31>;
interrupts = <0 284 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <1>;
qcom,num-ees = <2>;
};
slim_msm: slim@A5C0000 {
compatible = "qcom,slim-ngd-v1.5.0";
reg = <0xA5C0000 0x2C000>, <0xA66E000 0x1000>;
reg-names = "ctrl", "slimbus_remote_mem";
interrupts = <0 283 IRQ_TYPE_LEVEL_HIGH>;
qcom,apps-ch-pipes = <0x0>;
qcom,ea-pc = <0x3F0>;
dmas = <&slimbam 3>, <&slimbam 4>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msm_gpu: qcom,kgsl-3d0@5900000 { };
qcom_pmu: qcom,pmu {
compatible = "qcom,pmu";
qcom,pmu-events-tbl =
< 0x0008 0x0F 0xFF 0xFF >,
< 0x0011 0x0F 0xFF 0xFF >,
< 0x0017 0x0F 0xFF 0xFF >;
};
ddr_freq_table: ddr-freq-table {
qcom,freq-tbl =
< 200000 >,
< 300000 >,
< 451000 >,
< 547000 >,
< 681000 >,
< 768000 >,
< 1017000 >,
< 1353000 >,
< 1555000 >,
< 1804000 >,
< 2029000 >;
};
qcom_dcvs: qcom,dcvs {
compatible = "qcom,dcvs";
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom_ddr_dcvs_hw: ddr {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <0>;
qcom,bus-width = <4>; //CHECK
qcom,freq-tbl = <&ddr_freq_table>;
ddr_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI_CH0>;
};
};
};
bwmon_ddr: qcom,bwmon-ddr@4520300 {
compatible = "qcom,bwmon4";
reg = <0x4520300 0x300>, <0x4520200 0x200 >;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
qcom,count-unit = <0x10000>;
};
qcom_memlat: qcom,memlat {
compatible = "qcom,memlat";
ddr {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
qcom,sampling-path = <&ddr_dcvs_sp>;
qcom,miss-ev = <0x17>;
silver-compute {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,sampling-enabled;
qcom,compute-mon;
qcom,cpufreq-memfreq-tbl =
< 614400 547000 >,
< 864000 547000 >,
< 1363200 681000 >,
< 1708800 1353000 >;
};
};
};
};
#include "pm5100.dtsi"
#include "pm5100-rpm-regulator.dtsi"
#include "pm8010-rpm-regulator.dtsi"
#include "monaco-regulators.dtsi"
#include "monaco-pmic.dtsi"
#include "monaco-pinctrl.dtsi"
#include "monaco-qupv3.dtsi"
#include "monaco-coresight.dtsi"
#include "msm-arm-smmu-monaco.dtsi"
#include "monaco-dma-heaps.dtsi"
#include "monaco-gdsc.dtsi"
#include "monaco-usb.dtsi"
#include "monaco-thermal.dtsi"
#include "msm-rdbg-monaco.dtsi"
#include "monaco-walt.dtsi"
&gcc_camss_top_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_usb20_prim_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_vcodec0_gdsc {
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_venus_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&mdss_core_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gpu_cx_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gpu_gx_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&usb0 {
extcon = <&pm5100_charger>, <&eud>;
#io-channel-cells = <1>;
io-channels= <&pm5100_charger PSY_IIO_USB_REAL_TYPE>;
io-channel-names = "chg_type";
};
&qupv3_se1_i2c {
status = "ok";
tsc@24 {
compatible = "parade,pt_i2c_adapter";
reg = <0x24>;
status = "ok";
interrupt-parent = <&tlmm>;
interrupts = <80 0x2008>;
parade,adapter_id = "pt_i2c_adapter";
vcc_i2c-supply = <&L21A>;
vdd-supply = <&L29A>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend",
"pmx_ts_release";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
parade,core {
parade,name = "pt_core";
parade,irq_gpio = <&tlmm 13 0x2008>;
parade,rst_gpio = <&tlmm 12 0x00>;
parade,hid_desc_register = <1>;
/*
* PT_CORE_FLAG_NONE = 0x00
* PT_CORE_FLAG_POWEROFF_ON_SLEEP = 0x02
* PT_CORE_FLAG_RESTORE_PARAMETERS = 0x04
* PT_CORE_FLAG_DEEP_STANDBY = 0x08
* PT_CORE_FLAG_SKIP_SYS_SLEEP = 0x10
* PT_CORE_FLAG_SKIP_RUNTIME = 0x20
* PT_CORE_FLAG_SKIP_RESUME = 0x40
*/
parade,flags = <6>;
/* PT_CORE_EWG_NONE */
parade,easy_wakeup_gesture = <1>;
/* 0:AUTO 1:PIP1_ONLY 2:PIP2_CAPABLE*/
parade,config_dut_generation = <1>;
/* 0:False 1:True*/
parade,watchdog_force_stop = <0>;
/*
* PT_PANEL_ID_DISABLE = 0x00
* PT_PANEL_ID_BY_BL = 0x01
* PT_PANEL_ID_BY_SYS_INFO = 0x02
* PT_PANEL_ID_BY_MFG_DATA = 0x04
*/
parade,panel_id_support = <0>;
parade,btn_keys = <172 /* KEY_HOMEPAGE */
/* previously was KEY_HOME, new Android versions use KEY_HOMEPAGE */
139 /* KEY_MENU */
158 /* KEY_BACK */
217 /* KEY_SEARCH */
114 /* KEY_VOLUMEDOWN */
115 /* KEY_VOLUMEUP */
212 /* KEY_CAMERA */
116>; /* KEY_POWER */
parade,btn_keys-tag = <0>;
parade,mt {
parade,name = "pt_mt";
parade,inp_dev_name = "pt_mt";
/*
* PT_MT_FLAG_NONE = 0x00
* PT_MT_FLAG_FLIP = 0x08
* PT_MT_FLAG_INV_X = 0x10
* PT_MT_FLAG_INV_Y = 0x20
* PT_MT_FLAG_VKEYS = 0x40
*/
parade,flags = <0x08>;
parade,abs =
/* ABS_MT_POSITION_X, CY_ABS_MIN_X, CY_ABS_MAX_X, 0, 0 */
<0x35 0 880 0 0
/* ABS_MT_POSITION_Y, CY_ABS_MIN_Y, CY_ABS_MAX_Y, 0, 0 */
0x36 0 1280 0 0
/* ABS_MT_PRESSURE, CY_ABS_MIN_P, CY_ABS_MAX_P, 0, 0 */
0x3a 0 255 0 0
/* CY_IGNORE_VALUE, CY_ABS_MIN_W, CY_ABS_MAX_W, 0, 0 */
0xffff 0 255 0 0
/* ABS_MT_TRACKING_ID, CY_ABS_MIN_T, CY_ABS_MAX_T, 0, 0 */
0x39 0 15 0 0
/* ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0 */
0x30 0 255 0 0
/* ABS_MT_TOUCH_MINOR, 0, 255, 0, 0 */
0x31 0 255 0 0
/* ABS_MT_ORIENTATION, -127, 127, 0, 0 */
0x34 0xffffff81 127 0 0
/* ABS_MT_TOOL_TYPE, 0, MT_TOOL_MAX, 0, 0 */
0x37 0 1 0 0
/* ABS_DISTANCE, 0, 255, 0, 0 */
0x19 0 255 0 0>;
parade,vkeys_x = <720>;
parade,vkeys_y = <1280>;
parade,virtual_keys = /* KeyCode CenterX CenterY Width Height */
/* KEY_BACK */
<158 90 1360 160 180
/* KEY_MENU */
139 270 1360 160 180
/* KEY_HOMEPAGE */
172 450 1360 160 180
/* KEY SEARCH */
217 630 1360 160 180>;
};
parade,btn {
parade,name = "pt_btn";
parade,inp_dev_name = "pt_btn";
};
parade,proximity {
parade,name = "pt_proximity";
parade,inp_dev_name = "pt_proximity";
parade,abs =
<0x19 0 1 0 0>;
};
};
};
};
&qupv3_se6_2uart {
status = "ok";
};
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