b1cc355fcd
This change adds wlan opensource dtsi files for alor-kiwi and alor-wcn7750. Change-Id: Ibab85d6b48ca5852d6dd7d89f688a931fd2ccb08 CRs-Fixed: 4061525
156 lines
4.3 KiB
Plaintext
156 lines
4.3 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,alor.h>
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&tlmm {
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icnss_sw_ctrl: icnss_sw_ctrl {
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mux {
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pins = "gpio18";
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function = "wcn_sw_ctrl";
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};
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};
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};
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&soc {
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qcom,smp2p-wpss {
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smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
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qcom,entry-name = "wlan";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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smp2p_wlan_1_out: qcom,smp2p-wlan-1-out {
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qcom,entry-name = "wlan";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_wlan_2_in: qcom,smp2p-wlan-2-in {
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qcom,entry-name = "wlan_soc_wake";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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smp2p_wlan_2_out: qcom,smp2p-wlan-2-out {
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qcom,entry-name = "wlan_soc_wake";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_wlan_3_out: qcom,smp2p-wlan-3-out {
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qcom,entry-name = "wlan_ep_power_save";
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#qcom,smem-state-cells = <1>;
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};
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};
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icnss2_direct_link_iommu_group0: icnss2_direct_link_iommu_group0 {
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qcom,iommu-dma-addr-pool = <0x0 0xb0000000 0x0 0x10000000>;
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qcom,iommu-geometry = <0x0 0xb0000000 0x0 0x10010000>;
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qcom,iommu-dma = "fastmap";
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qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
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};
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icnss2: qcom,wcn7750 {
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compatible = "qcom,wcn7750";
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reg = <0x0 0x17010040 0x0 0x0>,
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<0x0 0xc0000000 0x0 0x10000>;
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reg-names = "msi_addr", "smmu_iova_ipa";
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qcom,rproc-handle = <&wpss_pas>;
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iommus = <&apps_smmu 0x1400 0x1>;
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wlan-en-gpio =<35>;
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host-sol-gpio =<95>;
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dev-sol-gpio =<17>;
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sw-ctrl-gpio =<18>;
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/* List of GPIOs to be setup for interrupt wakeup capable */
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mpm_wake_set_gpios = <18>;
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pinctrl-names = "sw_ctrl";
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pinctrl-0 = <&icnss_sw_ctrl>;
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interrupts = <GIC_SPI 896 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 897 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 898 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 899 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 900 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 901 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 902 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 903 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 904 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 905 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 906 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 907 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 908 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 909 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 910 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 911 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 912 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 913 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 914 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 915 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 916 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 917 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 918 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 919 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 920 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 921 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 923 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 924 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 925 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 926 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 927 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 928 IRQ_TYPE_EDGE_RISING>;
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qcom,iommu-group = <&icnss2_direct_link_iommu_group0>;
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dma-coherent;
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pin-ctrl-support;
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qcom,fw-prefix;
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qcom,wlan;
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tsens = "sys-therm-3";//TODO VERIFY from thermal team
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wcn-hw-version = "wcn7750";
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qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
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//TODO REGULATOR VOTING
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qcom,smem-states = <&smp2p_wlan_1_out 0>,
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<&smp2p_wlan_2_out 0>,
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<&smp2p_wlan_3_out 0>;
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qcom,smem-state-names = "wlan-smp2p-out",
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"wlan-soc-wake-smp2p-out",
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"wlan-ep-powersave-smp2p-out";
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qcom,qmp = <&aoss_qmp>;
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qcom,vreg_ol_cpr ="s2d";
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//TODO BUS BW
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icnss_cdev_apss: icnss_cdev1 {
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#cooling-cells = <2>;
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};
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icnss_cdev_wpss: icnss_cdev2 {
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#cooling-cells = <2>;
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};
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qcom,smp2p_map_wlan_1_in {
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interrupts-extended = <&smp2p_wlan_1_in 0 0>,
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<&smp2p_wlan_1_in 1 0>;
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interrupt-names = "qcom,smp2p-force-fatal-error",
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"qcom,smp2p-early-crash-ind";
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};
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qcom,smp2p_map_wlan_2_in {
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interrupts-extended = <&smp2p_wlan_2_in 0 0>;
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interrupt-names = "qcom,smp2p-soc-wake-ack";
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};
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};
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wlan_direct_link: qcom,icnss-direct-link {
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compatible = "qcom,icnss-direct-link";
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iommus = <&apps_smmu 0x100f 0x0>;
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qcom,iommu-group = <&icnss2_direct_link_iommu_group0>;
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dma-coherent;
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};
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};
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