b471e42ad0
DT snapshot from branch msm-5.15.c2
commit 8ae5ffe89e0f ("ARM: dts: msm: Add mdsp heap for mDSP compute").
Change-Id: If3e807289b6d981865430c4e1a45dabf236fa345
Signed-off-by: Naresh Kumar Lingagalla <quic_nlingaga@quicinc.com>
138 lines
3.2 KiB
Plaintext
138 lines
3.2 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&soc {
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/* GDSCs in GCC */
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gcc_camss_top_gdsc: qcom,gdsc@1458004 {
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compatible = "qcom,gdsc";
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reg = <0x1458004 0x4>;
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regulator-name = "gcc_camss_top_gdsc";
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status = "disabled";
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};
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gcc_emac0_gdsc: qcom,gdsc@145c004 {
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compatible = "qcom,gdsc";
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reg = <0x145c004 0x4>;
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regulator-name = "gcc_emac0_gdsc";
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status = "disabled";
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};
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gcc_pcie_0_gdsc: qcom,gdsc@145d004 {
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compatible = "qcom,gdsc";
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reg = <0x145d004 0x4>;
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regulator-name = "gcc_pcie_0_gdsc";
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status = "disabled";
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};
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gcc_usb20_prim_gdsc: qcom,gdsc@141c004 {
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compatible = "qcom,gdsc";
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reg = <0x141c004 0x4>;
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regulator-name = "gcc_usb20_prim_gdsc";
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status = "disabled";
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};
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gcc_usb30_prim_gdsc: qcom,gdsc@141a004 {
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compatible = "qcom,gdsc";
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reg = <0x141a004 0x4>;
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regulator-name = "gcc_usb30_prim_gdsc";
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status = "disabled";
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};
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gcc_vcodec0_gdsc: qcom,gdsc@14580ac {
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compatible = "qcom,gdsc";
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reg = <0x14580ac 0x4>;
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regulator-name = "gcc_vcodec0_gdsc";
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status = "disabled";
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};
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gcc_venus_gdsc: qcom,gdsc@1458088 {
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compatible = "qcom,gdsc";
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reg = <0x1458088 0x4>;
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regulator-name = "gcc_venus_gdsc";
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status = "disabled";
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};
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hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {
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compatible = "qcom,gdsc";
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reg = <0x147d078 0x4>;
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regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {
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compatible = "qcom,gdsc";
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reg = <0x147d074 0x4>;
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regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 {
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compatible = "qcom,gdsc";
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reg = <0x147d060 0x4>;
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regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c {
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compatible = "qcom,gdsc";
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reg = <0x147d07c 0x4>;
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regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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/* GDSCs in DISPCC */
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mdss_core_gdsc: qcom,gdsc@5f03000 {
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compatible = "qcom,gdsc";
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reg = <0x5f03000 0x4>;
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regulator-name = "mdss_core_gdsc";
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proxy-supply = <&mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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status = "disabled";
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};
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/* GDSCs in GPUCC */
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gpu_gx_sw_reset: syscon@5994008 {
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compatible = "syscon";
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reg = <0x5994008 0x4>;
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};
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gpu_cx_hw_ctrl: syscon@5994540 {
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compatible = "syscon";
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reg = <0x5994540 0x4>;
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};
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gpu_gx_domain_addr: syscon@5994508 {
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compatible = "syscon";
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reg = <0x5994508 0x4>;
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};
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gpu_cx_gdsc: qcom,gdsc@5994064 {
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compatible = "qcom,gdsc";
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reg = <0x5994064 0x4>;
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regulator-name = "gpu_cx_gdsc";
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hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
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qcom,gds-timeout = <500>;
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qcom,clk-dis-wait-val = <8>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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gpu_gx_gdsc: qcom,gdsc@599400c {
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compatible = "qcom,gdsc";
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reg = <0x599400c 0x4>;
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regulator-name = "gpu_gx_gdsc";
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sw-reset = <&gpu_gx_sw_reset>;
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domain-addr = <&gpu_gx_domain_addr>;
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qcom,reset-aon-logic;
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status = "disabled";
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};
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};
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