6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
47 lines
1.2 KiB
Plaintext
47 lines
1.2 KiB
Plaintext
Lantiq Synchronous Serial Controller (SSC) SPI master driver
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Required properties:
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- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
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"intel,lgm-spi"
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- #address-cells: see spi-bus.txt
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- #size-cells: see spi-bus.txt
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- reg: address and length of the spi master registers
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- interrupts:
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For compatible "intel,lgm-ssc" - the common interrupt number for
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all of tx rx & err interrupts.
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or
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For rest of the compatibles, should contain the "spi_rx", "spi_tx" and
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"spi_err" interrupt.
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Optional properties:
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- clocks: spi clock phandle
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- num-cs: see spi-bus.txt, set to 8 if unset
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- base-cs: the number of the first chip select, set to 1 if unset.
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Example:
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spi: spi@e100800 {
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compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
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reg = <0xE100800 0x100>;
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interrupt-parent = <&icu0>;
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interrupts = <22 23 24>;
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interrupt-names = "spi_rx", "spi_tx", "spi_err";
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#address-cells = <1>;
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#size-cells = <1>;
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num-cs = <6>;
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base-cs = <1>;
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};
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ssc0: spi@e0800000 {
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compatible = "intel,lgm-spi";
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reg = <0xe0800000 0x400>;
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interrupt-parent = <&ioapic1>;
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interrupts = <35 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cgu0 LGM_CLK_NGI>, <&cgu0 LGM_GCLK_SSC0>;
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clock-names = "freq", "gate";
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};
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