21931c9f8f
Add the dummy clock and gdsc handles for clients to be able to request on them for kera platform. Change-Id: I24fa8bf818483947760c8b87497b25bcf40be84c Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
528 lines
11 KiB
Plaintext
528 lines
11 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,cambistmclkcc-sun.h>
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#include <dt-bindings/clock/qcom,camcc-sun.h>
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#include <dt-bindings/clock/qcom,dispcc-tuna.h>
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#include <dt-bindings/clock/qcom,gcc-kera.h>
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#include <dt-bindings/clock/qcom,gpucc-kera.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
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#include <dt-bindings/clock/qcom,videocc-tuna.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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/ {
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model = "Qualcomm Technologies, Inc. Kera";
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compatible = "qcom,kera";
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qcom,msm-id = <659 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory {
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device_type = "memory";
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reg = <0 0 0 0>;
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};
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chosen: chosen {
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bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
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};
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reserved_memory: reserved-memory {};
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firmware: firmware {};
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aliases {};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU3>;
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};
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core1 {
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cpu = <&CPU4>;
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};
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core2 {
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cpu = <&CPU5>;
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};
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core3 {
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cpu = <&CPU6>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17100000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x17100000 0x10000>, /* GICD */
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<0x17180000 0x200000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@17420000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17420000 0x1000>;
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clock-frequency = <19200000>;
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frame@17421000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17421000 0x1000>,
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<0x17422000 0x1000>;
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};
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frame@17423000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17423000 0x1000>;
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status = "disabled";
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};
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frame@17425000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17425000 0x1000>;
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status = "disabled";
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};
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frame@17427000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17427000 0x1000>;
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status = "disabled";
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};
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frame@17429000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17429000 0x1000>;
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status = "disabled";
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};
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frame@1742b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742b000 0x1000>;
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status = "disabled";
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};
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frame@1742d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742d000 0x1000>;
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status = "disabled";
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};
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};
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tlmm: pinctrl@f000000 {
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compatible = "qcom,kera-tlmm";
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reg = <0xf000000 0x1000000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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ipcc_mproc: qcom,ipcc@406000 {
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compatible = "qcom,ipcc";
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reg = <0x406000 0x1000>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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clock-frequency = <76800000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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clock-output-names = "sleep_clk";
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#clock-cells = <0>;
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};
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pcie_0_pipe_clk: pcie_0_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_0_pipe_clk";
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#clock-cells = <0>;
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};
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pcie_1_pipe_clk: pcie_1_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_1_pipe_clk";
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#clock-cells = <0>;
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};
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ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "ufs_phy_rx_symbol_0_clk";
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#clock-cells = <0>;
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};
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ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "ufs_phy_rx_symbol_1_clk";
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#clock-cells = <0>;
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};
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ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "ufs_phy_tx_symbol_0_clk";
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#clock-cells = <0>;
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};
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usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
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#clock-cells = <0>;
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};
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};
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rpmhcc: clock-controller {
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compatible = "fixed-clock";
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clock-output-names = "rpmh_clocks";
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clock-frequency = <19200000>;
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#clock-cells = <1>;
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};
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cambistmclkcc: clock-controller@1760000 {
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compatible = "qcom,dummycc";
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clock-output-names = "cambistmclkcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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camcc: clock-controller@ade0000 {
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compatible = "qcom,dummycc";
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clock-output-names = "camcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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dispcc: clock-controller@af00000 {
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compatible = "qcom,dummycc";
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clock-output-names = "dispcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gcc: clock-controller@100000 {
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compatible = "qcom,dummycc";
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clock-output-names = "gcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gpucc: clock-controller@3d90000 {
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compatible = "qcom,dummycc";
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clock-output-names = "gpucc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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tcsrcc: clock-controller@1f40000 {
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compatible = "qcom,dummycc";
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clock-output-names = "tcsrcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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videocc: clock-controller@aaf0000 {
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compatible = "qcom,dummycc";
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clock-output-names = "videocc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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#include "tuna-gdsc.dtsi"
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&cam_cc_ipe_0_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&cam_cc_ofe_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&cam_cc_tfe_0_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&cam_cc_tfe_1_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&cam_cc_tfe_2_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&cam_cc_titan_top_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&disp_cc_mdss_core_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&disp_cc_mdss_core_int2_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&gcc_pcie_0_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&gcc_pcie_0_phy_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&gcc_pcie_1_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&gcc_pcie_1_phy_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&gcc_ufs_mem_phy_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&gcc_ufs_phy_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&gcc_usb30_prim_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&gcc_usb3_phy_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&gpu_cc_cx_gdsc_hw_ctrl {
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reg = <0x3d99124 0x4>;
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};
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&gpu_cc_cx_gdsc {
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compatible = "regulator-fixed";
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reg = <0x3d99110 0x4>;
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status = "ok";
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};
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&gpu_cc_gx_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&video_cc_mvs0_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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&video_cc_mvs0c_gdsc {
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compatible = "regulator-fixed";
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status = "ok";
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};
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#include "kera-pinctrl.dtsi"
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