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android_kernel_samsung_sm87…/qcom/sun-oemvm.dtsi
Kishore Kumar Ravi b228b1409c ARM: dts: msm: Add oemvm qrtr gunyah node for sun
Add the nodes for enable qrtr communication between primary vm and
oemvm on sun.

This adds platform devices and vdevice descriptions to start the
qrtr gunyah transport on both primary vm and oemvm device trees. This
also adds the device tree node to configure qrtr as node id 21 on oem
vm.

Change-Id: I1575853a67fe9edbcb751dbb71062b6da624d9be
Signed-off-by: Kishore Kumar Ravi <quic_kiskum@quicinc.com>
2023-11-20 12:50:36 +05:30

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
qcom,msm-id = <618 0x10000>;
interrupt-parent = <&vgic>;
chosen {
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce";
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
CPU0: cpu@0 {
compatible = "arm,armv8";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
cpu-idle-states = <&CPU_PWR_DWN
&CLUSTER_PWR_DWN>;
};
CPU1: cpu@100 {
compatible = "arm,armv8";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
cpu-idle-states = <&CPU_PWR_DWN
&CLUSTER_PWR_DWN>;
};
};
idle-states {
CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */
compatible = "arm,idle-state";
idle-state-name = "ret";
entry-latency-us = <93>;
exit-latency-us = <129>;
min-residency-us = <560>;
arm,psci-suspend-param = <0x00000004>;
status = "disabled";
};
CLUSTER_PWR_DWN: cl5 { /* C4+CL5 */
compatible = "arm,idle-state";
idle-state-name = "ret-pll-off";
entry-latency-us = <1964>;
exit-latency-us = <1901>;
min-residency-us = <24511>;
arm,psci-suspend-param = <0x01000054>;
status = "disabled";
};
};
qcom,vm-config {
compatible = "qcom,vm-1.0";
vm-type = "aarch64-guest";
boot-config = "fdt,unified";
os-type = "linux";
kernel-entry-segment = "kernel";
kernel-entry-offset = <0x0 0x0>;
vendor = "QTI";
image-name = "qcom,oemvm";
qcom,pasid = <0x0 0x22>;
qcom,qtee-config-info = "p=9,7C,8F,97,159,7F1;";
qcom,secdomain-ids = <49>;
qcom,primary-vm-index = <0>;
vm-uri = "vmuid/oemvm";
vm-guid = "847bfe26-0b12-5728-812a-06103f6bdec0";
vm-attrs = "crash-fatal", "context-dump";
memory {
#address-cells = <0x2>;
#size-cells = <0x0>;
/*
* IPA address linux image is loaded at. Must be within
* first 1GB due to memory hotplug requirement.
*/
base-address = <0x0 0x88800000 >;
};
segments {
config_cpio = <2>;
};
vcpus {
config = "/cpus";
affinity = "proxy";
affinity-map = <0x5 0x6>;
sched-priority = <0>; /* relative to PVM */
sched-timeslice = <2000>; /* in ms */
};
interrupts {
config = &vgic;
};
vdevices {
generate = "/hypervisor";
rm-rpc {
vdevice-type = "rm-rpc";
generate = "/hypervisor/qcom,resource-mgr";
console-dev;
message-size = <0x000000f0>;
queue-depth = <0x00000008>;
qcom,label = <0x1>;
};
virtio-mmio@0 {
vdevice-type = "virtio-mmio";
generate = "/virtio-mmio";
peer-default;
vqs-num = <0x1>;
push-compatible = "virtio,mmio";
dma-coherent;
dma_base = <0x0 0x0>;
memory {
qcom,label = <0x13>;
#address-cells = <0x2>;
base = <0x0 0xFFEFC000>;
};
};
swiotlb-shm {
vdevice-type = "shm";
generate = "/swiotlb";
push-compatible = "swiotlb";
peer-default;
dma_base = <0x0 0x4000>;
memory {
qcom,label = <0x14>;
#address-cells = <0x2>;
base = <0x0 0xFFF00000>;
};
};
test-dbl-oemvm {
vdevice-type = "doorbell";
generate = "/hypervisor/test-dbl-oemvm";
qcom,label = <0x5>;
peer-default;
};
test-dbl-oemvm-source {
vdevice-type = "doorbell-source";
generate = "/hypervisor/test-dbl-oemvm-source";
qcom,label = <0x5>;
peer-default;
};
test-msgq-oemvm {
vdevice-type = "message-queue-pair";
generate = "/hypervisor/test-msgq-oemvm-pair";
message-size = <0xf0>;
queue-depth = <0x8>;
qcom,label = <0x5>;
peer-default;
};
qrtr-shm {
vdevice-type = "shm-doorbell";
generate = "/hypervisor/qrtr-shm";
push-compatible = "qcom,qrtr-gunyah-gen";
peer-default;
memory {
qcom,label = <0x8>;
allocate-base;
};
};
};
};
firmware: firmware {
scm {
compatible = "qcom,scm";
};
};
soc: soc { };
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
vgic: interrupt-controller@16000000 {
compatible = "arm,gic-v3";
interrupt-controller;
#interrupt-cells = <0x3>;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x40000>;
reg = <0x16000000 0x10000>, /* GICD */
<0x16080000 0x200000>; /* GICR * 8 */
};
arch_timer: timer {
compatible = "arm,armv8-timer";
always-on;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
qcom,test-dbl-oemvm {
compatible = "qcom,gh-dbl";
qcom,label = <0x5>;
};
qcom,test-msgq-oemvm {
compatible = "qcom,gh-msgq-test";
gunyah-label = <0x5>;
affinity = <0>;
};
qcom,gh-qtimer@16805000 {
compatible = "qcom,gh-qtmr";
reg = <0x16805000 0x1000>;
reg-names = "qtmr-base";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "qcom,qtmr-intr";
qcom,secondary;
};
qcom,qrtr {
compatible = "qcom,qrtr";
qcom,node-id = <21>;
};
qrtr-gunyah {
compatible = "qcom,qrtr-gunyah";
gunyah-label = <8>;
};
};