50032b556d
Add context banks support for tuna Change-Id: Ib5a68c71da8211a8a6eaf17d72b46d4449d608f4 Signed-off-by: Patan Saddam <quic_psaddam@quicinc.com>
38 lines
1.1 KiB
Plaintext
38 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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fastrpc_gen_pool_region: fastrpc_gen_pool_region {
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iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>;
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};
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fastrpc_compute_cb1: compute-cb@13 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <11>;
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iommus = <&apps_smmu 0xC0B 0x0>;
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memory-region = <&fastrpc_gen_pool_region>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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qcom,iova-best-fit;
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qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
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qrtr-gen-pool = <&fastrpc_compute_cb1>;
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frpc-gen-addr-pool = <0x8000 0x9000>;
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pd-type = <4>; /* SECURE_STATICPD */
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};
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qrtr-genpool {
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compatible = "qcom,qrtr-genpool";
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gen-pool = <&fastrpc_compute_cb1>;
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interrupt-parent = <&ipcc_mproc_ns1>;
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interrupts = <IPCC_CLIENT_CDSP 0 IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_CDSP 1 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>,
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<&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>;
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};
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};
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