a42a681f5d
Add DWC3 USB controller device-tree nodes for sdxkova. Change-Id: I9a44ad5d49dfb8bdadca04696c8580e283b5f2ec Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
69 lines
1.7 KiB
Plaintext
69 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,sdx75-gcc.h>
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&soc {
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usb: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x0 0xa600000 0x0 0x100000>;
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reg-names = "core_base";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 10 IRQ_TYPE_EDGE_RISING>,
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<&pdc 9 IRQ_TYPE_EDGE_RISING>,
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<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event_irq", "dp_hs_phy_irq",
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"dm_hs_phy_irq", "ss_phy_irq";
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qcom,use-pdc-interrupts;
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USB3_GDSC-supply = <&gcc_usb30_gdsc>;
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clocks = <&gcc GCC_USB30_MASTER_CLK>,
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<&gcc GCC_USB30_SLV_AHB_CLK>,
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<&gcc GCC_USB30_MSTR_AXI_CLK>,
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<&gcc GCC_USB30_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SLEEP_CLK>;
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clock-names = "core_clk", "iface_clk",
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"bus_aggr_clk", "utmi_clk",
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"sleep_clk";
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resets = <&gcc GCC_USB30_BCR>;
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reset-names = "core_reset";
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qcom,sleep-clk-bcr;
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,core-clk-rate-disconnected = <133333333>;
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dwc3: dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xa600000 0x0 0xd93c>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb_nop_phy>, <&usb_nop_phy>;
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snps,has-lpm-erratum;
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snps,is-utmi-l1-suspend;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis_u2_susphy_quirk;
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snps,hird-threshold = /bits/ 8 <0x10>;
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tx-fifo-resize;
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/* set host mode interrupt moderation to 1 us */
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imod-interval-ns = <1000>;
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maximum-speed = "super-speed-plus";
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usb-role-switch;
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dr_mode = "peripheral";
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};
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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};
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