a191ae962a
Add initial device tree support for parrot/ravelin vm target.
This is a snapshot of dtsi files as of KP.1.0
'commit <370d8eab7cc6> ("Merge "ARM: dts: qcom:
Disable cnss-kiwi SOL on anorak platform"")'.
Change-Id: Iaf69c882974f38b69d9edd671d675f14dfb9774d
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
147 lines
3.5 KiB
Plaintext
147 lines
3.5 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "waipio-vm.dtsi"
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/ {
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qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
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<633 0x10000>, <634 0x10000>, <638 0x10000>;
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interrupt-parent = <&vgic>;
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qcom,vm-config {
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iomemory-ranges = <0x0 0x0a28000 0x0 0x0a28000 0x0 0x4000 0x0
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0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
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0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
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0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1
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0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1
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0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;
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gic-irq-ranges = <325 325>; /* PVM->SVM IRQ transfer */
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vdevices {
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gvsock-message-queue-pair {
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status = "disabled";
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};
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};
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};
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};
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&soc {
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/delete-node/ interrupt-controller@17100000;
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qcom,spmi@c42d000 {
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status = "disabled";
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};
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vgic: interrupt-controller@17200000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17200000 0x10000>, /* GICD */
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<0x17260000 0x100000>; /* GICR * 8 */
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};
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pinctrl@f000000 {
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compatible = "qcom,parrot-vm-tlmm";
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gpios = /bits/ 16 <>;
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qcom,gpios-reserved = <0 1 2 3 38>;
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};
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tlmm-vm-mem-access {
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tlmm-vm-gpio-list = <>;
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};
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apps-smmu@15000000 {
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qcom,actlr =
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/* Display and camera clients, +0 PF */
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<0x800 0x7ff 0x1>,
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<0x2000 0xE0 0x1>,
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<0x2100 0x60 0x1>,
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/* For video clients, +3 PF */
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<0x2180 0x27 0x103>,
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/* NSP clients, +15PF */
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<0x1000 0x7ff 0x303>;
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};
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/delete-node/ qup_common_iommu_group;
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/delete-node/ qcom,qupv3_0_geni_se@9c0000;
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/delete-node/ qcom,gpi-dma@900000;
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/delete-node/ i2c@990000;
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/delete-node/ spi@990000;
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qup_iommu_group: qup_common_iommu_group {
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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};
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gpi_dma1: qcom,gpi-dma@a00000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0xa00000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0x418 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <12>;
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qcom,gpii-mask = <0x40>;
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qcom,ev-factor = <2>;
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qcom,gpi-ee-offset = <0x10000>;
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qcom,le-vm;
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status = "ok";
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};
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/* QUPv3_1 wrapper instance */
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qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0xac0000 0x2000>;
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iommus = <&apps_smmu 0x418 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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status = "ok";
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/* TUI over I2C */
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qupv3_se9_i2c: i2c@a8c000 {
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compatible = "qcom,i2c-geni";
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reg = <0xa8c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&gpi_dma1 0 3 3 64 0>,
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<&gpi_dma1 1 3 3 64 0>;
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dma-names = "tx", "rx";
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qcom,le-vm;
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status = "disabled";
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};
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qupv3_se9_spi: spi@a8c000 {
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compatible = "qcom,spi-geni";
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reg = <0xa8c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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dmas = <&gpi_dma1 0 3 1 64 0>,
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<&gpi_dma1 1 3 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,le-vm;
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status = "disabled";
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};
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};
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};
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