34 lines
1019 B
Plaintext
34 lines
1019 B
Plaintext
#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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msm_fastrpc: qcom,msm_fastrpc {
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compatible = "qcom,msm-fastrpc-compute";
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qcom,rpc-latency-us = <235>;
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qcom,fastrpc-gids = <2908>;
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qcom,qos-cores = <0 1 2 3>;
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fastrpc_compute_cb1: qcom,msm_fastrpc_compute_cb1 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0xC0B 0x0>;
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qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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qrtr-gen-pool = <&fastrpc_compute_cb1>;
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frpc-gen-addr-pool = <0x8000 0x9000>;
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pd-type = <4>; /* SECURE_STATICPD */
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};
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};
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qrtr-genpool {
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compatible = "qcom,qrtr-genpool";
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gen-pool = <&fastrpc_compute_cb1>;
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interrupt-parent = <&ipcc_mproc_ns1>;
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interrupts = <IPCC_CLIENT_CDSP 0 IRQ_TYPE_EDGE_RISING>,
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<IPCC_CLIENT_CDSP 1 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>,
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<&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>;
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};
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};
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