f61c034cdf
This change removes support for display clock scaling through mmrm is not supported in kera target. Change-Id: Idb83968784dcd1e6cabc5bc107a5bd8013612686 Signed-off-by: Mahadevan <quic_mahap@quicinc.com> Signed-off-by: lnxdisplay <lnxdisplay@localhost>
332 lines
9.4 KiB
Plaintext
332 lines
9.4 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/clock/qcom,dispcc-tuna.h>
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#include <dt-bindings/clock/qcom,gcc-kera.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
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#include "kera-sde-common.dtsi"
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#include <dt-bindings/interconnect/qcom,kera.h>
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#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
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&soc {
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ext_disp: qcom,msm-ext-disp {
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compatible = "qcom,msm-ext-disp";
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ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
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compatible = "qcom,msm-ext-disp-audio-codec-rx";
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};
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};
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qcom_msmhdcp: qcom,msm_hdcp {
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compatible = "qcom,msm-hdcp";
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};
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sde_dp_pll: qcom,dp_pll@88ea000 {
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compatible = "qcom,dp-pll-4nm-v1.1";
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#clock-cells = <1>;
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};
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sde_dp: qcom,dp_display@af54000 {
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cell-index = <0>;
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compatible = "qcom,dp-display";
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status = "ok";
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usb-phy = <&usb_qmp_dp_phy>;
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qcom,ext-disp = <&ext_disp>;
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usb-controller = <&usb0>;
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qcom,altmode-dev = <&altmode 0>;
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qcom,dp-aux-switch = <&wcd_usbss>;
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reg = <0xaf54000 0x104>,
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<0xaf54200 0x0c0>,
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<0xaf55000 0x770>,
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<0xaf56000 0x09c>,
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<0x88eaa00 0x200>,
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<0x88ea200 0x200>,
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<0x88ea600 0x200>,
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<0x88ea000 0x200>,
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<0x88e8000 0x020>,
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<0xaee1000 0x034>,
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<0xaf57000 0x09c>,
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<0xaf09000 0x014>;
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reg-names = "dp_ahb", "dp_aux", "dp_link",
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"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
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"dp_pll", "usb3_dp_com", "hdcp_physical",
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"dp_p1", "gdsc";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <12 0>;
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#clock-cells = <1>;
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clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&tcsrcc TCSR_USB3_CLKREF_EN>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
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<&sde_dp_pll 0>,
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<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
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<&sde_dp_pll 1>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
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clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src",
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"core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent",
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"link_iface_clk", "pixel_clk_rcg", "pixel_parent",
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"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk";
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qcom,dp-pll = <&sde_dp_pll>;
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qcom,phy-version = <0x600>;
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qcom,aux-cfg0-settings = [20 00];
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qcom,aux-cfg1-settings = [24 13];
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qcom,aux-cfg2-settings = [28 A4];
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qcom,aux-cfg3-settings = [2c 00];
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qcom,aux-cfg4-settings = [30 0a];
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qcom,aux-cfg5-settings = [34 26];
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qcom,aux-cfg6-settings = [38 0a];
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qcom,aux-cfg7-settings = [3c 03];
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qcom,aux-cfg8-settings = [40 b7];
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qcom,aux-cfg9-settings = [44 03];
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qcom,max-pclk-frequency-khz = <675000>;
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qcom,widebus-enable;
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qcom,dsc-feature-enable;
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qcom,fec-feature-enable;
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qcom,dsc-continuous-pps;
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qcom,qos-cpu-mask = <0xf>;
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qcom,qos-cpu-latency-us = <300>;
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vdda-1p2-supply = <&L4B>;
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vdda-0p9-supply = <&L7K>;
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vdda_usb-0p9-supply = <&L7K>;
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vdd_mx-supply = <&VDD_MXA_LEVEL>;
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dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
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qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>,
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<0x11 0x1e 0x1f 0xff>,
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<0x16 0x1f 0xff 0xff>,
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<0x1f 0xff 0xff 0xff>;
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qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>,
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<0x00 0x0e 0x15 0xff>,
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<0x00 0x0e 0xff 0xff>,
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<0x02 0xff 0xff 0xff>;
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qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>,
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<0x09 0x19 0x1f 0xff>,
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<0x10 0x1f 0xff 0xff>,
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<0x1f 0xff 0xff 0xff>;
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qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>,
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<0x02 0x0e 0x16 0xff>,
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<0x02 0x11 0xff 0xff>,
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<0x04 0xff 0xff 0xff>;
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1320000>;
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qcom,supply-enable-load = <30000>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,phy-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,phy-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-0p9";
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qcom,supply-min-voltage = <912000>;
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qcom,supply-max-voltage = <950000>;
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qcom,supply-enable-load = <114000>;
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qcom,supply-disable-load = <0>;
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};
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qcom,phy-supply-entry@1 {
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reg = <1>;
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qcom,supply-name = "vdda_usb-0p9";
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qcom,supply-min-voltage = <880000>;
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qcom,supply-max-voltage = <950000>;
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qcom,supply-enable-load = <2500>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,pll-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,pll-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdd_mx";
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qcom,supply-min-voltage =
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<RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,supply-max-voltage =
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<RPMH_REGULATOR_LEVEL_MAX>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition {
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iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>,
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<&smmu_sde_unsec 0xFC800000 0x02B00000>,
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<&smmu_sde_sec 0x0 0x00020000>;
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};
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smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
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compatible = "qcom,smmu_sde_unsec";
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iommus = <&apps_smmu 0x800 0x2>;
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memory-region = <&smmu_sde_iommu_region_partition>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-earlymap; /* for cont-splash */
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dma-coherent;
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clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "mdp_core_clk";
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};
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smmu_sde_sec: qcom,smmu_sde_sec_cb {
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compatible = "qcom,smmu_sde_sec";
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iommus = <&apps_smmu 0x801 0x0>;
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memory-region = <&smmu_sde_iommu_region_partition>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xa>;
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clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "mdp_core_clk";
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};
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sde_cesta: qcom,sde_cesta@0x0af30000 {
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cell-index = <0>;
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compatible = "qcom,sde-cesta";
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reg = <0x0af20000 0x850>,
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<0xaf30000 0x60>,
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<0xaf31000 0x30>,
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<0xaf32000 0x30>,
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<0xaf33000 0x30>,
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<0xaf34000 0x30>,
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<0xaf35000 0x30>,
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<0xaf36000 0x30>,
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<0xaf0f000 0x10>;
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reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5",
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"disp_cc";
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clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
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<&dispcc DISP_CC_XO_CLK_SRC>;
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clock-names = "branch_clk", "core_clk", "xo";
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clock-rate = <660000000 660000000 19200000>;
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clock-max-rate = <660000000 660000000 19200000>;
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interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0
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&mc_virt SLAVE_EBI1_DISP_CRM_HW_0>,
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<&mmss_noc MASTER_MDP_DISP_CRM_HW_1
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&mc_virt SLAVE_EBI1_DISP_CRM_HW_1>,
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<&mmss_noc MASTER_MDP_DISP_CRM_HW_2
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&mc_virt SLAVE_EBI1_DISP_CRM_HW_2>,
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<&mmss_noc MASTER_MDP_DISP_CRM_HW_3
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&mc_virt SLAVE_EBI1_DISP_CRM_HW_3>,
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<&mmss_noc MASTER_MDP_DISP_CRM_HW_4
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&mc_virt SLAVE_EBI1_DISP_CRM_HW_4>,
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<&mmss_noc MASTER_MDP_DISP_CRM_HW_5
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&mc_virt SLAVE_EBI1_DISP_CRM_HW_5>,
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<&mmss_noc MASTER_MDP_DISP_CRM_SW_0
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&mc_virt SLAVE_EBI1_DISP_CRM_SW_0>;
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interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1",
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"qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3",
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"qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5",
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"qcom,sde-data-bus-sw-0";
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power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
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};
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};
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&mdss_mdp {
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clocks =
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
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clock-names = "gcc_bus",
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"iface_clk", "vsync_clk", "lut_clk";
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clock-rate = <0 0 19200000 660000000>;
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clock-max-rate = <0 0 19200000 660000000>;
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qcom,hw-fence-sw-version = <0x1>;
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qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;
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qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys";
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/* data and reg bus scale settings */
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interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,
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<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_DISPLAY_CFG>;
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interconnect-names = "qcom,sde-data-bus0",
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"qcom,sde-ebi-bus", "qcom,sde-reg-bus";
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qcom,sde-has-idle-pc;
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qcom,sde-ib-bw-vote = <2500000 0 1600000>;
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qcom,sde-dspp-ltm-version = <0x00010003>;
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/* offsets are based off dspp 0, 1, 2, and 3 */
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qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300>;
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};
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&mdss_dsi0 {
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vdda-1p2-supply = <&L4B>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
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};
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&mdss_dsi1 {
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vdda-1p2-supply = <&L4B>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_ESC1_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
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};
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&mdss_dsi_phy0 {
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vdda-0p9-supply = <&L2B>;
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qcom,panel-allow-phy-poweroff;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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pll_codes_region = <&dsi_pll_codes_data>;
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};
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&mdss_dsi_phy1 {
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vdda-0p9-supply = <&L2B>;
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qcom,panel-allow-phy-poweroff;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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pll_codes_region = <&dsi_pll_codes_data>;
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};
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