8894c3d7b3
Add DT bindings for SPI which provides the resource management details for the SPI geni msm driver. Change-Id: Ifcaccf747ee2efe41fba6d77660456916dcc099b Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@quicinc.com>
112 lines
2.6 KiB
YAML
112 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/qcom,spi-msm-geni.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies Inc GENI based Serial Peripheral Interface (SPI)
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maintainers:
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- Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
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description:
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GENI based Qualcomm Technologies Inc Universal Peripheral version 5 (QUPv3)
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Serial Peripheral Interface (SPI)
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The QUP v3 core is a GENI based AHB slave that provides a common data path
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(an output FIFO and an input FIFO) for serial peripheral interface (SPI) mini-core.
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SPI in master mode supports up to 50MHz, up to four chip selects, programmable
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data path from 4 bits to 32 bits and numerous protocol variants.
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allOf:
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- $ref: /schemas/spi/spi-controller.yaml#
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properties:
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compatible:
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const: qcom,spi-geni
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clocks:
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maxItems: 1
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clock-names:
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const: se-clk
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pinctrl-0: true
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pinctrl-1: true
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pinctrl-names:
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minItems: 1
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items:
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- const: default
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- const: sleep
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: tx
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- const: rx
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interconnects:
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minItems: 2
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maxItems: 3
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interconnect-names:
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minItems: 2
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items:
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- const: qup-core
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- const: qup-config
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- const: qup-memory
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interrupts:
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maxItems: 1
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reg:
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maxItems: 1
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reg-names:
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maxItems: 1
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spi-max-frequency:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- pinctrl-names
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- spi-max-frequency
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/interconnect/qcom,sun.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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qupv3_se0_spi: spi@a80000 {
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compatible = "qcom,spi-geni";
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reg = <0xa80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
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<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
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<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep>;
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dmas = <&gpi_dma1 0 0 1 64 0>,
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<&gpi_dma1 1 0 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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};
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...
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