a3a111ed95
Increase the number of pipe clock toggles that will occur after phystatus goes high at the output of the PHY during L1SS/P2 entry in PCS_PCIE_POWER_STATE_CONFIG6 register, so that if the phy and controller goes out of sync this may help us. The number of pipe clock toggles is equal to (4*value)+1. Change-Id: I7a31882f18879ef990825aa2d978fc7f39233472 Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
300 lines
7.6 KiB
Plaintext
300 lines
7.6 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/gpio/gpio.h>
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&soc {
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pcie0: pcie@1c00000 {
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compatible = "qcom,pci-msm";
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device_type = "pci";
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reg = <0x01c00000 0x3000>,
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<0x01c06000 0x2000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>,
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<0x01D07000 0x7000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
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"pcie_sm";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3d00000>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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msi-map = <0x0 &gic_its 0x1400 0x1>,
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<0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */
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perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
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wake-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_perst_default
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&pcie0_clkreq_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_perst_default
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&pcie0_clkreq_sleep
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&pcie0_wake_default>;
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gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_NOM
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RPMH_REGULATOR_LEVEL_NOM
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100000000>;
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interconnect-names = "icc_path";
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interconnects = <&pcie_noc MASTER_PCIE_3_PCIE_CRM_HW_0
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&mc_virt SLAVE_EBI1_PCIE_CRM_HW_0>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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dma-coherent;
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qcom,smmu-sid-base = <0x1400>;
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iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
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<0x100 &apps_smmu 0x1401 0x1>;
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qcom,boot-option = <0x1>;
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qcom,aux-clk-freq = <20>; /* 19.2 MHz */
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qcom,l1-2-th-scale = <2>;
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qcom,l1-2-th-value = <150>;
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qcom,ep-latency = <10>;
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qcom,num-parf-testbus-sel = <0xb9>;
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qcom,pcie-phy-ver = <94>;
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qcom,phy-status-offset = <0x414>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x440>;
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qcom,phy-sequence = <0x0440 0x03 0x0
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0x00c0 0x01 0x0
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0x00cc 0x62 0x0
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0x00d0 0x02 0x0
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0x0060 0xf8 0x0
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0x0064 0x01 0x0
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0x0000 0x93 0x0
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0x0004 0x01 0x0
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0x00e0 0x90 0x0
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0x00e4 0x82 0x0
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0x00f4 0x07 0x0
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0x0070 0x02 0x0
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0x0010 0x02 0x0
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0x0074 0x16 0x0
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0x0014 0x16 0x0
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0x0078 0x36 0x0
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0x0018 0x36 0x0
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0x0110 0x08 0x0
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0x00bc 0x0a 0x0
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0x0120 0x42 0x0
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0x0080 0x04 0x0
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0x0084 0x0d 0x0
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0x0020 0x0a 0x0
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0x0024 0x1a 0x0
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0x0088 0x41 0x0
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0x0028 0x34 0x0
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0x0090 0xab 0x0
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0x0094 0xaa 0x0
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0x0098 0x01 0x0
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0x0030 0x55 0x0
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0x0034 0x55 0x0
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0x0038 0x01 0x0
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0x0140 0x14 0x0
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0x0164 0x34 0x0
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0x003c 0x01 0x0
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0x001c 0x04 0x0
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0x0174 0x16 0x0
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0x01bc 0x0f 0x0
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0x0170 0xa0 0x0
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0x13a4 0x38 0x0
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0x12dc 0x11 0x0
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0x1360 0xbf 0x0
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0x1364 0xbf 0x0
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0x1368 0xb7 0x0
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0x136c 0xea 0x0
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0x135c 0x3f 0x0
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0x1374 0x09 0x0
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0x1378 0x49 0x0
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0x137c 0x1b 0x0
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0x1380 0x8f 0x0
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0x1370 0xd1 0x0
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0x1388 0x09 0x0
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0x138c 0x49 0x0
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0x1390 0x1b 0x0
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0x1394 0x8f 0x0
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0x1384 0xd1 0x0
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0x12c4 0x3e 0x0
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0x12c8 0x1e 0x0
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0x12cc 0xd2 0x0
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0x1208 0x09 0x0
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0x1214 0x05 0x0
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0x124c 0x08 0x0
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0x1250 0x08 0x0
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0x12d8 0x09 0x0
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0x1318 0x1c 0x0
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0x131c 0x60 0x0
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0x12f8 0x07 0x0
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0x13f8 0x08 0x0
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0x1800 0x00 0x0
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0x1084 0x35 0x0
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0x108c 0x10 0x0
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0x1090 0x31 0x0
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0x1094 0x7f 0x0
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0x10e4 0x02 0x0
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0x1040 0x08 0x0
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0x103c 0x14 0x0
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0x1ba4 0x38 0x0
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0x1adc 0x11 0x0
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0x1b60 0xbf 0x0
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0x1b64 0xbf 0x0
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0x1b68 0xb7 0x0
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0x1b6c 0xea 0x0
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0x1b5c 0x3f 0x0
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0x1b74 0x09 0x0
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0x1b78 0x49 0x0
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0x1b7c 0x1b 0x0
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0x1b80 0x8f 0x0
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0x1b70 0xd1 0x0
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0x1b88 0x09 0x0
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0x1b8c 0x49 0x0
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0x1b90 0x1b 0x0
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0x1b94 0x8f 0x0
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0x1b84 0xd1 0x0
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0x1ac4 0x3e 0x0
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0x1ac8 0x1e 0x0
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0x1acc 0xd2 0x0
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0x1a08 0x09 0x0
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0x1a14 0x05 0x0
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0x1a4c 0x08 0x0
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0x1a50 0x08 0x0
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0x1ad8 0x09 0x0
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0x1b18 0x1c 0x0
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0x1b1c 0x60 0x0
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0x1af8 0x07 0x0
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0x1bf8 0x08 0x0
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0x1884 0x35 0x0
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0x188c 0x10 0x0
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0x1890 0x31 0x0
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0x1894 0x7f 0x0
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0x18e4 0x02 0x0
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0x1840 0x08 0x0
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0x183c 0x14 0x0
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0x04dc 0x05 0x0
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0x0588 0x77 0x0
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0x0598 0x0b 0x0
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0x08a4 0x1e 0x0
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0x08f4 0x27 0x0
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0x05e4 0x0f 0x0
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0x080c 0x1d 0x0
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0x0814 0x07 0x0
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0x0820 0xc1 0x0
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0x0894 0x00 0x0
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0x08f8 0x1f 0x0
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0x05d0 0x8c 0x0
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0x0568 0x17 0x0
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0x0570 0x2e 0x0
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0x0400 0x00 0x0
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0x0444 0x03 0x0>;
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qcom,drv-name = "cesta";
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qcom,drv-l1ss-timeout-us = <5000>;
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qcom,pcie-clkreq-offset = <0x2C48>;
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qcom,pcie-clkreq-pin = <103>;
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qcom,pcie-sm-branch-offset = <0x1000>;
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qcom,pcie-sm-start-offset = <0x1090>;
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qcom,pcie-sm-seq = <0x1c018081>, <0x70074002>, <0x50028000>,
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<0x28007003>, <0x80804002>, <0x70021c01>,
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<0x18001802>, <0x70005000>, <0x10004000>,
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<0x80814002>, <0x18001c01>, <0x1c018080>,
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<0x0000100>;
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qcom,pcie-sm-branch-seq = <0x4>, <0x1c>, <0x24>, <0x2c>, <0x0>,
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<0x0>, <0x0>;
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qcom,pcie-sm-debug = <0x1040>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_VAL */
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<0x1048>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_MASK */
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<0x1050>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_VAL */
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<0x1058>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_MASK */
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<0x1060>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_VAL */
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<0x1068>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_MASK */
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<0x1070>, /* PCIE_SMs_SEQ_PWR_CTRL_STATUS */
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<0x1078>, /* PCIE_SMs_SEQ_WAIT_EVENT_STATUS */
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<0x1080>, /* PCIE_SMs_SEQ_BR_EVENT_STATUS */
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<0x1088>, /* PCIE_SMs_SEQ_PC_VAL */
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<0x1090>, /* PCIE_SMs_SEQ_START */
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<0x1094>, /* PCIE_SMs_CLKREQ_GATE */
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<0x1098>, /* PCIE_SMs_CLKREQ_UNGATE */
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<0x109C>; /* PCIE_SMs_CLKREQ_GATE_REQ_STATUS */
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@16110040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17110040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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};
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