467330472c
Add snapshot of dcvs dt bindings as of qcom-6.1
commit 96af901712d3 ("dt-bindings: soc: qcom: Document
CRMB and CRMC regs").
Change-Id: I305f06bee1895feabec2b85b2c5ed4fa80895f83
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Signed-off-by: Gurbir Arora <quic_gurbaror@quicinc.com>
58 lines
1.9 KiB
YAML
58 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/qcom/qcom,pmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. (QTI) PMU Monitor Driver
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maintainers:
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- avajid@quicinc.com <quic_avajid@quicinc.com>
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- gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
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description: |
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The Qualcomm Technologies, Inc. PMU Driver provides an interface to request
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for per-CPU performance counters that are available on some QTI chipsets.
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properties:
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compatible:
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const: qcom,pmu
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qcom,long-counter:
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description:
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Specify if the pmu counters are long (64 bit) counters.
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type: boolean
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qcom,pmu-events-tbl:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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A list of the pmu events to be configured on the cpus. The first column in
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the table contains the event id and the second column contains a bit mask
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(cpumask) of cpus for which the event should be configured on. The third
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column contains the AMU id for events that are present as part of AMU
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counters. The list of ids can be found in enum amu_counters
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(include/soc/qcom/pmu_lib.h). 0xFF represents an invalid id. The fourth
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column represents the index in enum cpucp_ev_idx
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(include/linux/scmi_pmu.h), which is a shared enum between hlos and cpucp.
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This helps maintain the sequence of events when pmu hardware ids or cached
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counts are shared between hlos and cpucp. 0xFF represents an invalid
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index, which means this event is not supposed to be shared between hlos
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and cpucp.
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required:
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- compatible
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- qcom,pmu-events-tbl
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examples:
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- |
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qcom,pmu {
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compatible = "qcom,pmu";
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qcom,long-counter;
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qcom,pmu-events-tbl =
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< 0x0008 0xFF 0x02 0x02 >,
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< 0x0011 0xFF 0x01 0x01 >,
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< 0x0017 0xFF 0xFF 0x04 >,
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< 0x002A 0xFF 0xFF 0xFF >,
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< 0x1000 0xFF 0xFF 0xFF >;
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};
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