8eb1a2d085
Document crm_b_pt register. Change-Id: Iec8522f68d516bd26c59924be0fe68be13d3a5e8 Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
150 lines
3.6 KiB
YAML
150 lines
3.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/qcom/qcom,crm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. (QTI) CESTA Resource Manager
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maintainers:
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- Maulik Shah <quic_mkshah@quicinc.com>
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description:
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Support for communication with the hardened-CRM blocks. A set of HW and
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SW client DRVs in CRM provides interface to vote desired power state of
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resources local to a subsystem.
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properties:
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label:
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$ref: /schemas/types.yaml#/definitions/string-array
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oneOf:
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- description: Specifies the name of the CRM.
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items:
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- enum:
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- cam_crm
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- pcie_crm
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- disp_crm
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compatible:
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oneOf:
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- description: v1 of CESTA HW
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items:
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- enum:
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- qcom,cam-crm
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- qcom,pcie-crm
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- description: v2 of CESTA HW
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items:
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- enum:
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- qcom,cam-crm-v2
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- qcom,pcie-crm-v2
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- qcom,disp-crm-v2
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reg:
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minItems: 6
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reg-names:
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items:
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- const: base
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- const: crm_b
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- const: crm_b_pt
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- const: crm_c
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- const: crm_v
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- const: common
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interrupts:
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maxItems: 1
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interrupt-names:
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maxItems: 1
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qcom,hw-drv-ids:
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description: List of HW DRV IDs.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 3
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items:
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minimum: 0
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maximum: 2
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qcom,sw-drv-ids:
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description: List of SW DRV IDs.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 2
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items:
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minimum: 0
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maximum: 1
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clocks:
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items:
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- description: Bus Clock
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required:
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- label
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- compatible
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- reg
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- reg-names
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- clocks
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oneOf:
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- required:
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- qcom,hw-drv-ids
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- required:
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- qcom,sw-drv-ids
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if:
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required:
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- qcom,sw-drv-ids
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then:
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required:
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- interrupts
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- interrupt-names
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additionalProperties: false
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examples:
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# Example of Camera CRM device with HW DRVs
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,camcc-sun.h>
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cam_crm: crm@adcb000 {
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label = "cam_crm";
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compatible = "qcom,cam-crm";
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reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd600 0x2000>,
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<0xadcf600 0x700>, <0xadcfd00 0x100>;
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reg-names = "base", "crm_b", "crm_c", "crm_v", "common";
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clocks = <&camcc CAM_CC_DRV_AHB_CLK>;
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qcom,hw-drv-ids = <0 1 2>;
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};
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# Example of PCIe CRM device with SW DRVs
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie_crm: crm@1d01000 {
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label = "pcie_crm";
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compatible = "qcom,pcie-crm";
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reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03800 0x2000>,
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<0x1d05800 0x700>, <0x1d05f00 0x100>;
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reg-names = "base", "crm_b", "crm_c", "crm_v", "common";
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interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "pcie_crm";
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clocks = <&pcie_0_pipe_clk>;
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qcom,sw-drv-ids = <0>;
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};
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# Example of Disp CRM device with SW DRVs
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,dispcc-sun.h>
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disp_crm: crm@af21000 {
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label = "disp_crm";
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compatible = "qcom,disp-crm-v2";
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reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27800 0x2000>,
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<0xaf29800 0x700>, <0xaf29f00 0x100>;
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reg-names = "base", "crm_b", "crm_c", "crm_v", "common";
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interrupts = <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "disp_crm";
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
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qcom,sw-drv-ids = <0>;
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};
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...
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