6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
66 lines
2.1 KiB
YAML
66 lines
2.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Unisoc DRM master device
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maintainers:
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- Kevin Tang <kevin.tang@unisoc.com>
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description: |
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The Unisoc DRM master device is a virtual device needed to list all
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DPU devices or other display interface nodes that comprise the
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graphics subsystem.
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Unisoc's display pipeline have several components as below description,
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multi display controllers and corresponding physical interfaces.
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For different display scenarios, dpu0 and dpu1 maybe binding to different
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encoder.
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E.g:
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dpu0 and dpu1 both binding to DSI for dual mipi-dsi display;
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dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display;
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+-----------------------------------------+
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| |
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| +---------+ |
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+----+ | +----+ +---------+ |DPHY/CPHY| | +------+
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| +----->+dpu0+--->+MIPI|DSI +--->+Combo +----->+Panel0|
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|AXI | | +----+ +---------+ +---------+ | +------+
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| | | ^ |
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| | | | |
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| | | +-----------+ |
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| | | | |
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|APB | | +--+-+ +-----------+ +---+ | +------+
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| +----->+dpu1+--->+DisplayPort+--->+PHY+--------->+Panel1|
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| | | +----+ +-----------+ +---+ | +------+
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+----+ | |
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+-----------------------------------------+
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properties:
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compatible:
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const: sprd,display-subsystem
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ports:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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maxItems: 1
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description:
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Should contain a list of phandles pointing to display interface port
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of DPU devices.
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required:
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- compatible
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- ports
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additionalProperties: false
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examples:
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- |
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display-subsystem {
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compatible = "sprd,display-subsystem";
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ports = <&dpu_out>;
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};
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