6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
51 lines
1.1 KiB
YAML
51 lines
1.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module Binding
|
|
|
|
maintainers:
|
|
- Jacky Bai <ping.bai@nxp.com>
|
|
|
|
description: |
|
|
On i.MX8ULP, The clock sources generation, distribution and management is
|
|
under the control of several CGCs & PCCs modules. The PCC modules control
|
|
software reset, clock selection, optional division and clock gating mode
|
|
for peripherals.
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- fsl,imx8ulp-pcc3
|
|
- fsl,imx8ulp-pcc4
|
|
- fsl,imx8ulp-pcc5
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
'#clock-cells':
|
|
const: 1
|
|
|
|
'#reset-cells':
|
|
const: 1
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- '#clock-cells'
|
|
- '#reset-cells'
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
# Peripheral Clock Control Module node:
|
|
- |
|
|
clock-controller@292d0000 {
|
|
compatible = "fsl,imx8ulp-pcc3";
|
|
reg = <0x292d0000 0x10000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|