Add the bindings for the msm_qmp driver in YAML. Change-Id: I4fdddf7f88c2ba8777f0c674238b19e496e093c3 Signed-off-by: Richard Maina <quic_rmaina@quicinc.com>
135 lines
4.0 KiB
YAML
135 lines
4.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/arm/msm/msm_qmp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: QMP Driver binding
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maintainers:
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- Richard Maina <quic_rmaina@quicinc.com>
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description: |+
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The QTI mailbox protocol (QMP for short) mechanism provides an
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ultra-light weight IPC mechanism with an ultimate code-size goal of 1-2KB.
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This transport is considered as an alternative to subsystems whose code-size
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restriction makes it impractical to include Link.The mailbox transport
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distinguishes between two communicating processors as-
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- Micro-core (uCore) – This is for all practical purposes the master who
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determines the communication protocol & features supported over the current
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IPC mechanism.
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- Macro-core (abbreviated as MCore) – This code adapts to the protocol
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version and features supported by the micro core.
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If no such distinction can be made between the two communicating cores then
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either can be picked to be the micro-core.
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This communication transport has further limitations and if further
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enhancements are required, GLink should be considered.
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- Only one channel per edge allowed.
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- Only one message allowed to be in flight at any given time.
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- The maximum message size which can be transmitted as a unit is fixed statically.
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properties:
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compatible:
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items:
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- const: qcom,qmp-mbox
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label:
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$ref: '/schemas/types.yaml#/definitions/string'
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maxItems: 1
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description:
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The name of the remote proc this link connects to.
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reg:
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minItems: 1
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description:
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The location and size of shared memory.
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The irq register base address for triggering interrupts.
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reg-names:
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minItems: 1
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description:
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'msgram' the string to identify the shared memory region.
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'irq-reg-base' the string to identify the irq register region.
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qcom,irq-mask:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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maxItems: 1
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description:
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The bitmask to trigger an interrupt.
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mboxes:
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description:
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Handle to outgoing interrupt if not using irq-reg-base.
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interrupt:
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$ref: '/schemas/types.yaml#/definitions/uint32-array'
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minItems: 1
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description:
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The receiving interrupt line.
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mbox-desc-offset:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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maxItems: 1
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description:
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Offset of mailbox descriptor from start of the msgram.
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priority:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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maxItems: 1
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description: The priority of this mailbox compared to other mailboxes.
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'#mbox-cells':
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- const: 1
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description:
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Common mailbox binding property to identify the number of cells
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required for the mailbox specifier, should be 1.
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qcom,early-boot:
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$ref: '/schemas/types.yaml#/definitions/boolean'
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description:
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Bool to indicate that this remote proc will boot before QMP.
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mbox-offset:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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maxItems: 1
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description:
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offset of the mcore mailbox from the offset of msgram. If this
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property is not used, qmp will use the configuration
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provided by the ucore.
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mbox-size:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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maxItems: 1
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description:
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size of the mcore mailbox. If this property is not used, qmp will
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use the configuration provided by the ucore.
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required:
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- compatible
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- label
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- reg
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- reg-names
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- qcom,irq-mask
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- mboxes
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- interrupt
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- mbox-desc-offset
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- number of mbox-cells
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examples:
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- |
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qmp_aop: qcom,qmp-aop {
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compatible = "qcom,qmp-mbox";
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label = "aop";
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qcom,early-boot;
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reg = <0xc300000 0x100000>,
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<0x1799000C 0x4>;
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reg-names = "msgram", "irq-reg-base";
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qcom,irq-mask = <0x1>;
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interrupt = <0 389 1>;
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mbox-desc-offset = <0x100>;
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priority = <1>;
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mbox-offset = <0x500>;
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mbox-size = <0x400>;
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#mbox-cells = <1>;
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};
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