548c30e08a
tuna-wcn7750 This change adds wlan related dt files for tuna-wcn7750 which has icnss and wpss dtsi node enabled. Change-Id: I59167fbff63c7a54836452f6f29e4ede14f3f4c7 CRs-Fixed: 3940163
171 lines
5.0 KiB
Plaintext
171 lines
5.0 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,tuna.h>
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&soc {
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qcom,smp2p-wpss {
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smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
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qcom,entry-name = "wlan";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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smp2p_wlan_1_out: qcom,smp2p-wlan-1-out {
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qcom,entry-name = "wlan";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_wlan_2_in: qcom,smp2p-wlan-2-in {
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qcom,entry-name = "wlan_soc_wake";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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smp2p_wlan_2_out: qcom,smp2p-wlan-2-out {
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qcom,entry-name = "wlan_soc_wake";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_wlan_3_out: qcom,smp2p-wlan-3-out {
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qcom,entry-name = "wlan_ep_power_save";
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#qcom,smem-state-cells = <1>;
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};
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};
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icnss2: qcom,wcn7750 {
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compatible = "qcom,wcn7750";
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reg = <0x17110040 0x0>,
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<0xc0000000 0x10000>;
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reg-names = "msi_addr", "smmu_iova_ipa";
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qcom,rproc-handle = <&wpss_pas>;
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iommus = <&apps_smmu 0x1480 0x1>;
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wlan-en-gpio =<35>;
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host-sol-gpio =<132>;
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dev-sol-gpio =<32>;
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wlan-sw-ctrl-gpio =<80>;
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interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
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qcom,iommu-dma = "fastmap";
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qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
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qcom,iommu-dma-addr-pool = <0xb0000000 0x10000000>;
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qcom,iommu-geometry = <0xb0000000 0x10010000>;
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dma-coherent;
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qcom,fw-prefix;
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qcom,wlan;
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tsens = "sys-therm-3";
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qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
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qcom,smem-states = <&smp2p_wlan_1_out 0>,
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<&smp2p_wlan_2_out 0>,
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<&smp2p_wlan_3_out 0>;
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qcom,smem-state-names = "wlan-smp2p-out",
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"wlan-soc-wake-smp2p-out",
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"wlan-ep-powersave-smp2p-out";
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qcom,qmp = <&aoss_qmp>;
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qcom,vreg_ol_cpr ="s3b";
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interconnects =
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<&pcie_anoc MASTER_PCIE_0 &pcie_anoc SLAVE_ANOC_PCIE_GEM_NOC>,
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<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
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interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
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qcom,icc-path-count = <2>;
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qcom,bus-bw-cfg-count = <9>;
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qcom,bus-bw-cfg =
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/** ICC Path 1 **/
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<0 0>, /* no vote */
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/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
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<2250 1200000>,
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/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
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<7500 1200000>,
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/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
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<30000 1200000>,
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/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
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<100000 1200000>,
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/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
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<175000 3224000>,
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/* ultra high: DBS mode snoc/anoc: 403 Mhz */
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<312500 3224000>,
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/* super high: DBS mode snoc/anoc: 533 Mhz */
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<587500 4264000>,
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/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
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<7500 1600000>,
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/** ICC Path 2 **/
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<0 0>,
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/* idle: 0-18 Mbps ddr: 451.2 MHz */
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<2250 2188800>,
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/* low: 18-60 Mbps ddr: 451.2 MHz */
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<7500 2188800>,
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/* medium: 60-240 Mbps ddr: 451.2 MHz */
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<30000 2188800>,
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/* high: 240-1200 Mbps ddr: 451.2 MHz */
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<100000 2188800>,
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/* very high: > 1200 Mbps ddr: 1555 MHz */
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<175000 6220800>,
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/* ultra high: DBS mode ddr: 2092 MHz */
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<312500 8368000>,
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/* super high: DBS mode ddr: 3.2 GHz */
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<587500 12800000>,
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/* low (latency critical): 18-60 Mbps ddr: 451.2 MHz */
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<7500 2188800>;
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icnss_cdev_apss: qcom,icnss_cdev1 {
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#cooling-cells = <2>;
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};
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icnss_cdev_wpss: qcom,icnss_cdev2 {
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#cooling-cells = <2>;
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};
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qcom,smp2p_map_wlan_1_in {
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interrupts-extended = <&smp2p_wlan_1_in 0 0>,
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<&smp2p_wlan_1_in 1 0>;
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interrupt-names = "qcom,smp2p-force-fatal-error",
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"qcom,smp2p-early-crash-ind";
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};
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qcom,smp2p_map_wlan_2_in {
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interrupts-extended = <&smp2p_wlan_2_in 0 0>;
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interrupt-names = "qcom,smp2p-soc-wake-ack";
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};
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};
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};
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