689ef8fa7f
Describe the available dma-buf memory pools on tuna-vm. Change-Id: Ia2bb3fff1f76a04c4f8a14b51917b59d029f8d5e Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
337 lines
7.4 KiB
Plaintext
337 lines
7.4 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-tuna.h>
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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qcom,msm-id = <681 0x10000>, <655 0x10000>;
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interrupt-parent = <&vgic>;
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chosen {
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bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce";
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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CPU0: cpu@0 {
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN
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&CLUSTER_PWR_DWN>;
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};
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CPU1: cpu@100 {
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN
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&CLUSTER_PWR_DWN>;
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};
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};
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idle-states {
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CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */
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compatible = "arm,idle-state";
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status = "disabled";
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};
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CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */
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compatible = "arm,idle-state";
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status = "disabled";
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};
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};
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qcom,vm-config {
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compatible = "qcom,vm-1.0";
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vm-type = "aarch64-guest";
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boot-config = "fdt,unified";
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os-type = "linux";
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kernel-entry-segment = "kernel";
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kernel-entry-offset = <0x0 0x0>;
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vendor = "QTI";
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image-name = "qcom,trustedvm";
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qcom,pasid = <0x0 0x1c>;
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qcom,qtee-config-info = "p=3,9,C,39,77,78,7C,8F,96,97,C8,FE,10C,11B,159,199,47E,7F1,CDF;";
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qcom,secdomain-ids = <45>;
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qcom,primary-vm-index = <0>;
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vm-uri = "vmuid/trusted-ui";
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vm-guid = "598085da-c516-5b25-a9c1-927a02819770";
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qcom,sensitive;
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vm-attrs = "context-dump", "crash-restart";
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/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
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* QUP1_SE4: GPII5 : IRQ_316
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* QUP2_SE7: GPII5 : IRQ_625
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*/
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gic-irq-ranges = <316 316
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625 625 /* PVM->SVM IRQ transfer */
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279 279>;
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memory {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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/*
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* IPA address linux image is loaded at. Must be within
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* first 1GB due to memory hotplug requirement.
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*/
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base-address = <0x0 0x88800000 >;
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};
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segments {
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config_cpio = <2>;
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};
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vcpus {
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config = "/cpus";
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affinity = "proxy";
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affinity-map = <0x5 0x6>;
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sched-priority = <0>; /* relative to PVM */
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sched-timeslice = <2000>; /* in ms */
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};
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interrupts {
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config = &vgic;
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};
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vdevices {
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generate = "/hypervisor";
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minidump {
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vdevice-type = "minidump";
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push-compatible = "qcom,minidump_rm";
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minidump_allowed;
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};
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rm-rpc {
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vdevice-type = "rm-rpc";
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generate = "/hypervisor/qcom,resource-mgr";
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console-dev;
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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qcom,label = <0x1>;
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};
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virtio-mmio@0 {
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vdevice-type = "virtio-mmio";
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generate = "/virtio-mmio";
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peer-default;
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vqs-num = <0x1>;
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push-compatible = "virtio,mmio";
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dma-coherent;
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dma_base = <0x0 0x0>;
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memory {
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qcom,label = <0x11>; //for persist.img
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#address-cells = <0x2>;
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base = <0x0 0xDA6F8000>;
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};
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};
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virtio-mmio@1 {
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vdevice-type = "virtio-mmio";
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generate = "/virtio-mmio";
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peer-default;
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vqs-num = <0x2>;
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push-compatible = "virtio,mmio";
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dma-coherent;
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dma_base = <0x0 0x4000>;
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memory {
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qcom,label = <0x10>; //for system.img
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#address-cells = <0x2>;
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base = <0x0 0xDA6FC000>;
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};
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};
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virtio-mmio@2 {
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vdevice-type = "virtio-mmio";
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patch = "/soc/virtio-mmio";
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peer-default;
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vqs-num = <0x3>;
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push-compatible = "virtio,mmio";
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dma-coherent;
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dma_base = <0x0 0x8000>;
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memory {
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qcom,label = <0x15>; //for virtio-vsock
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#address-cells = <0x2>;
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base = <0x0 0xDA700000>;
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};
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};
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swiotlb-shm {
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vdevice-type = "shm";
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generate = "/swiotlb";
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push-compatible = "swiotlb";
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peer-default;
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dma_base = <0x0 0x14000>;
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memory {
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qcom,label = <0x12>;
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#address-cells = <0x2>;
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base = <0x0 0xDA70c000>;
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};
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};
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vrtc {
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vdevice-type = "vrtc-pl031";
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peer-default;
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allocate-base;
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};
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gpiomem0 {
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vdevice-type = "iomem";
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patch = "/soc/tlmm-vm-mem-access";
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push-compatible = "qcom,tlmm-vm-mem-access";
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peer-default;
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memory {
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qcom,label = <0x8>;
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qcom,mem-info-tag = <0x3>;
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allocate-base;
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};
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};
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};
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};
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firmware: firmware {
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qcom_scm: qcom_scm {
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compatible = "qcom,scm";
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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compatible = "qcom,dummycc";
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clock-output-names = "gcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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virtio-mmio {
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wakeup-source;
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};
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vm_tlmm_irq: vm-tlmm-irq@0 {
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compatible = "qcom,tlmm-vm-irq";
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reg = <0x0 0x0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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tlmm: pinctrl@f000000 {
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compatible = "qcom,tuna-vm-tlmm";
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reg = <0x0F000000 0x1000000>;
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interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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/* Valid pins */
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gpios = /bits/ 16 <86 87 98 97 16 17 18 19 161 162 100 44 45 46 47 88 14 126 77 78 189 176>;
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};
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tlmm-vm-mem-access {
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compatible = "qcom,tlmm-vm-mem-access";
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tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
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&tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
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&tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
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&tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
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};
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tlmm-vm-test {
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compatible = "qcom,tlmm-vm-test";
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pinctrl-names = "active", "sleep";
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pinctrl-0 = <&qupv3_se1_7i2c_active>;
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pinctrl-1 = <&qupv3_se1_7i2c_sleep>;
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tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
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&tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
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&tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
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&tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
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};
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pinctrl@f000000 {
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qupv3_se1_7i2c_pins: qupv3_se1_7i2c_pins {
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qupv3_se1_7i2c_active: qupv3_se1_7i2c_active {
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mux {
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pins = "gpio44";
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function = "qup2_se7_l0";
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};
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config {
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pins = "gpio44";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se1_7i2c_sleep: qupv3_se1_7i2c_sleep {
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mux {
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pins = "gpio44";
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function = "gpio";
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};
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config {
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pins = "gpio44";
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drive-strength = <2>;
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};
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};
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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vgic: interrupt-controller@17100000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x17100000 0x10000>, /* GICD */
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<0x17180000 0x200000>; /* GICR * 8 */
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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always-on;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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qcom_smcinvoke {
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compatible = "qcom,smcinvoke";
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};
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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qcom,custom-bridge-size = <64>;
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qcom,support-hypervisor;
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};
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};
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#include "msm-arm-smmu-tuna-vm.dtsi"
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#include "tuna-vm-dma-heaps.dtsi"
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