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68698774fe5656168d2bab50dc66031c4110c8e4
android_kernel_samsung_sm87…/gpu/tuna-gpu-pwrlevels.dtsi
Rohit Jadhav 68698774fe Merge commit '9f996a9f8e9c6ca6081ab03b7f9d6a5e3ab11537' into gfx-devicetree-oss.lnx.1.0.r1-rel 
Change-Id: If47c5cf1c599c4d88f9a188829e1b70e6b481889
Signed-off-by: Rohit Jadhav <quic_rbjadhav@quicinc.com>
2025-03-09 07:31:52 +05:30

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* ACD Control register values */
#define ACD_LEVEL_TURBO_L2 0xa02f5ffd
#define ACD_LEVEL_TURBO_L1 0xa8285ffd
#define ACD_LEVEL_TURBO 0x88295ffd
#define ACD_LEVEL_NOM_L1 0xa8295ffd
#define ACD_LEVEL_NOM 0x882a5ffd
#define ACD_LEVEL_SVS_L2 0x882a5ffd
#define ACD_LEVEL_SVS_L1 0xa82a5ffd
#define ACD_LEVEL_SVS 0xa82c5ffd
#define ACD_LEVEL_LOW_SVS 0xc02c5ffd
#define ACD_LEVEL_LOW_SVS_D1 0xc02c5ffd
&msm_gpu {
/* Power levels */
qcom,gpu-pwrlevel-bins {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels-bins";
/*
* The bins need to match based on speed bin first and then SKU.
* Keep pwrlevel bins sorted in ascending order of the fmax of the bins.
*/
qcom,gpu-pwrlevels-0 {
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <9>;
qcom,speed-bin = <0>;
/* Turbo_L2 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1150000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L2>;
};
/* Turbo_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
};
/* Turbo */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <937000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <10>;
qcom,bus-min = <9>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_TURBO>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <873000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <763000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <688000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <644000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <510000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <6>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <362000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <264000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
};
};
qcom,gpu-pwrlevels-1 {
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <8>;
qcom,speed-bin = <0xd8>;
/* Turbo_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1025000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
};
/* Turbo */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <937000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <10>;
qcom,bus-min = <9>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_TURBO>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <873000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <763000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <688000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <644000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <510000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <362000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <264000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
};
};
qcom,gpu-pwrlevels-2 {
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <9>;
qcom,speed-bin = <0xf2>;
/* Turbo_L2 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1150000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L2>;
};
/* Turbo_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
};
/* Turbo */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <937000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <10>;
qcom,bus-min = <9>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_TURBO>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <873000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <763000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <688000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <644000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <510000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <362000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <264000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
};
};
};
};
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