629a5369ba
git-subtree-dir: qcom/mmrm git-subtree-mainline:1b15f14402git-subtree-split:40cf8f841b
108 lines
4.7 KiB
Plaintext
108 lines
4.7 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&soc {
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msm_mmrm_test: qcom,mmrm-test {
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compatible = "qcom,msm-mmrm-test", "qcom,sun-mmrm-test";
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status = "disable";
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/* Clock info */
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clock-names =
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"cam_cc_camnoc_rt_axi_clk_src",
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"cam_cc_csid_clk_src",
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"cam_cc_icp_0_clk_src",
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"cam_cc_icp_1_clk_src",
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"cam_cc_ife_lite_clk_src",
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"cam_cc_ipe_nps_clk_src",
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"cam_cc_jpeg_clk_src",
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"cam_cc_ofe_clk_src",
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"cam_cc_tfe_0_clk_src",
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"cam_cc_tfe_1_clk_src",
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"cam_cc_tfe_2_clk_src",
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"cam_cc_fast_ahb_clk_src",
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"cam_cc_slow_ahb_clk_src",
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"cam_cc_cci_0_clk_src",
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"cam_cc_cci_1_clk_src",
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"cam_cc_cci_2_clk_src",
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"cam_cc_cre_clk_src",
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"cam_cc_csi0phytimer_clk_src",
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"cam_cc_csi1phytimer_clk_src",
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"cam_cc_csi2phytimer_clk_src",
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"cam_cc_csi3phytimer_clk_src",
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"cam_cc_csi4phytimer_clk_src",
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"cam_cc_csi5phytimer_clk_src",
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"cam_cc_cphy_rx_clk_src",
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"cam_cc_ife_lite_csid_clk_src",
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"eva_cc_mvs0_clk_src",
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"disp_cc_mdss_mdp_clk_src",
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"video_cc_mvs0_clk_src";
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clocks =
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<&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>,
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<&camcc CAM_CC_CSID_CLK_SRC>,
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<&camcc CAM_CC_ICP_0_CLK_SRC>,
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<&camcc CAM_CC_ICP_1_CLK_SRC>,
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<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
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<&camcc CAM_CC_IPE_NPS_CLK_SRC>,
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<&camcc CAM_CC_JPEG_CLK_SRC>,
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<&camcc CAM_CC_OFE_CLK_SRC>,
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<&camcc CAM_CC_TFE_0_CLK_SRC>,
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<&camcc CAM_CC_TFE_1_CLK_SRC>,
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<&camcc CAM_CC_TFE_2_CLK_SRC>,
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<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
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<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
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<&camcc CAM_CC_CCI_0_CLK_SRC>,
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<&camcc CAM_CC_CCI_1_CLK_SRC>,
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<&camcc CAM_CC_CCI_2_CLK_SRC>,
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<&camcc CAM_CC_CRE_CLK_SRC>,
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<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
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<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
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<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
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<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
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<&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
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<&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
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<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
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<&evacc EVA_CC_MVS0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
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<&videocc VIDEO_CC_MVS0_CLK_SRC>;
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/*
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* clock_data : domain, clock-ID,
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* rate-LOWSVS, rate-SVS, rate-SVS_L1, rate-NOM, rate-TURBO,
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* num_hw_blocks, hw_drv_instances, num_pwr_states
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*/
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clock_data =
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<0x1 CAM_CC_CAMNOC_RT_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000 1 0 0>,
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<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 1 0 0>,
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<0x1 CAM_CC_ICP_0_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>,
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<0x1 CAM_CC_ICP_1_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>,
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<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000 1 0 0>,
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<0x1 CAM_CC_IPE_NPS_CLK_SRC 475000000 575000000 675000000 825000000 825000000 1 0 0>,
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<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>,
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<0x1 CAM_CC_OFE_CLK_SRC 484000000 586000000 688000000 841000000 841000000 1 0 0>,
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<0x1 CAM_CC_TFE_0_CLK_SRC 480000000 630000000 716000000 833000000 833000000 1 0 0>,
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<0x1 CAM_CC_TFE_1_CLK_SRC 480000000 630000000 716000000 833000000 833000000 1 0 0>,
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<0x1 CAM_CC_TFE_2_CLK_SRC 480000000 630000000 716000000 833000000 833000000 1 0 0>,
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<0x1 CAM_CC_FAST_AHB_CLK_SRC 300000000 300000000 300000000 400000000 400000000 1 0 0>,
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<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000 1 0 0>,
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<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>,
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<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>,
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<0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>,
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<0x1 CAM_CC_CRE_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
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<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
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<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
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<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
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<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
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<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
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<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
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<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000 10 0 0>,
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<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>,
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<0x1 EVA_CC_MVS0_CLK_SRC 1200000000 1350000000 1500000000 1650000000 1650000000 1 0 0>,
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<0x1 DISP_CC_MDSS_MDP_CLK_SRC 207000000 337000000 417000000 532000000 575000000 1 0 0>,
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<0x1 VIDEO_CC_MVS0_CLK_SRC 1014000000 1260000000 1332000000 1600000000 1890000000 1 0 0>;
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};
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};
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