6292886f04
Update tlmm-vm-gpio-list for ravelin vm.
Change-Id: Ic70f6a2334f81063ddc16ea368e1095de0a890fa
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
(cherry picked from commit ac8961a7a5)
141 lines
3.4 KiB
Plaintext
141 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "waipio-vm.dtsi"
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/ {
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qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>;
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interrupt-parent = <&vgic>;
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qcom,vm-config {
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iomemory-ranges = <0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0
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0x0 0x0928000 0x0 0x0928000 0x0 0x4000 0x0
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0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
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0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
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0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1
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0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1>;
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gic-irq-ranges = <282 282>; /* PVM->SVM IRQ transfer */
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vdevices {
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gvsock-message-queue-pair {
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status = "disabled";
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};
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};
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};
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};
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&soc {
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/delete-node/ interrupt-controller@17100000;
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qcom,spmi@c42d000 {
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status = "disabled";
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};
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vgic: interrupt-controller@17200000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17200000 0x10000>, /* GICD */
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<0x17260000 0x100000>; /* GICR * 8 */
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};
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tlmm: pinctrl@f000000 {
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compatible = "qcom,ravelin-vm-tlmm";
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gpios = /bits/ 16 <92 93>;
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};
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tlmm-vm-mem-access {
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tlmm-vm-gpio-list = <&tlmm 92 0 &tlmm 93 0>;
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};
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apps-smmu@15000000 {
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qcom,actlr =
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/* Display and camera clients, +0 PF */
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<0x1900 0x3F 0x1>,
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<0x1800 0xFF 0x1>,
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<0x800 0x7FF 0x1>,
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/* For video clients, +3 PF */
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<0x1980 0x3F 0x103>;
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};
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/delete-node/ qup_common_iommu_group;
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/delete-node/ qcom,qupv3_0_geni_se@9c0000;
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/delete-node/ qcom,gpi-dma@900000;
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/delete-node/ i2c@990000;
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/delete-node/ spi@990000;
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qup_iommu_group: qup_common_iommu_group {
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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};
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gpi_dma0: qcom,gpi-dma@900000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x900000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0x178 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <12>;
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qcom,gpii-mask = <0x40>;
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qcom,ev-factor = <2>;
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qcom,gpi-ee-offset = <0x10000>;
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qcom,le-vm;
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status = "ok";
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};
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/* QUPv3_0 wrapper instance */
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qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x9c0000 0x2000>;
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iommus = <&apps_smmu 0x178 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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status = "ok";
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/* Legacy Touch over I2C */
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qupv3_se1_i2c: i2c@984000 {
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compatible = "qcom,i2c-geni";
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reg = <0x984000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&gpi_dma0 0 1 3 64 0>,
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<&gpi_dma0 1 1 3 64 0>;
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dma-names = "tx", "rx";
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qcom,le-vm;
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status = "disabled";
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};
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qupv3_se1_spi: spi@984000 {
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compatible = "qcom,spi-geni";
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reg = <0x984000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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dmas = <&gpi_dma0 0 1 1 64 0>,
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<&gpi_dma0 1 1 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,le-vm;
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status = "disabled";
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};
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};
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};
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