6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
61 lines
1.6 KiB
YAML
61 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
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maintainers:
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- Rahul Tanwar <rtanwar@maxlinear.com>
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description: |
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Intel's Advanced Programmable Interrupt Controller (APIC) is a
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family of interrupt controllers. The APIC is a split
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architecture design, with a local component (LAPIC) integrated
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into the processor itself and an external I/O APIC. Local APIC
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(lapic) receives interrupts from the processor's interrupt pins,
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from internal sources and from an external I/O APIC (ioapic).
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And it sends these to the processor core for handling.
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See [1] Chapter 8 for more details.
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Many of the Intel's generic devices like hpet, ioapic, lapic have
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the ce4100 name in their compatible property names because they
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first appeared in CE4100 SoC.
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This schema defines bindings for I/O APIC interrupt controller.
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[1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
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properties:
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compatible:
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const: intel,ce4100-ioapic
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reg:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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additionalProperties: false
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examples:
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- |
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ioapic1: interrupt-controller@fec00000 {
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compatible = "intel,ce4100-ioapic";
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reg = <0xfec00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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