60fb428708
Sync state will remove the disp_cc device vote once the device driver probe is complete. It removes the DSI clock vote early for continuous splash usecase because DSI driver takes its vote in component binding instead of device driver probe. It is better to keep disp_cc vote for components till respective device probe complete and they register themselves to master component. This change adds disp_cc vote for smmu_sde_unsec, smmu_sde_sec, sde_wb1 and sde_wb2 devices to retain vote till bind_all API is called. Change-Id: Ie6e39cb53c4fdd93a1ce7d07a0fc99a250235902 Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
321 lines
8.2 KiB
Plaintext
321 lines
8.2 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "sun-sde.dtsi"
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#include "sun-sde-display-common.dtsi"
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#include <dt-bindings/clock/qcom,dispcc-sun.h>
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&pm8550_gpios {
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display_panel_avdd_default: display_panel_avdd_default {
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pins = "gpio11";
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function = "normal";
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input-disable;
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output-enable;
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bias-disable;
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power-source = <1>;
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qcom,drive-strength = <3>;
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};
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};
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&soc {
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sde_wb1: qcom,wb-display@1 {
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compatible = "qcom,wb-display";
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cell-index = <0>;
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label = "wb_display1";
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clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "mdp_core_clk";
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};
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sde_wb2: qcom,wb-display@2 {
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compatible = "qcom,wb-display";
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cell-index = <1>;
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label = "wb_display2";
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clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "mdp_core_clk";
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};
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display_panel_avdd: display_gpio_regulator@1 {
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compatible = "qti-regulator-fixed";
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regulator-name = "display_panel_avdd";
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regulator-min-microvolt = <5500000>;
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regulator-max-microvolt = <5500000>;
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regulator-enable-ramp-delay = <233>;
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gpio = <&pm8550_gpios 11 0>;
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enable-active-high;
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regulator-boot-on;
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proxy-supply = <&display_panel_avdd>;
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qcom,proxy-consumer-enable;
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pinctrl-names = "default";
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};
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disp_rdump_memory: disp_rdump_region@0xd5500000 {
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reg = <0xfc800000 0x00800000>;
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label = "disp_rdump_region";
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};
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};
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&reserved_memory {
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splash_memory: splash_region {
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reg = <0x0 0xfc800000 0x0 0x02b00000>;
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label = "cont_splash_region";
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};
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/*
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* Demura memory regions are to be commented out if
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* feature not in use.
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*/
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demura_memory_0: demura_region_0 {
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reg = <0x0 0x0 0x0 0x0>;
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label = "demura hfc region 0";
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};
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demura_memory_1: demura_region_1 {
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reg = <0x0 0x0 0x0 0x0>;
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label = "demura hfc region 1";
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};
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};
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&sde_dsi {
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clocks = <&mdss_dsi_phy0 0>,
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<&mdss_dsi_phy0 1>,
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<&mdss_dsi_phy1 0>,
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<&mdss_dsi_phy1 1>,
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/*
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* Currently the dsi clock handles are under the dsi
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* controller DT node. As soon as the controller probe
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* finishes, the dispcc sync state can get called before
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* the dsi_display probe potentially disturbing the clock
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* votes for cont_splash use case. Hence we are no longer
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* protected by the component model in this case against the
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* disp cc sync state getting triggered after the dsi_ctrl
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* probe. To protect against this incorrect sync state trigger
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* add this dummy MDP clk vote handle to the dsi_display
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* DT node. Since the dsi_display driver does not parse
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* MDP clock nodes, no actual vote shall be added and this
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* change is done just to satisfy sync state requirements.
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*/
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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/*
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* The esync clk RCG is only necessary here to set its parent
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* to the pll dsi clk, which also needs to be available at the
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* point that its known whether the clock will be used. After
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* updating the parent, this clock handle is no longer needed.
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*/
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<&dispcc DISP_CC_ESYNC0_CLK_SRC>;
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clock-names = "pll_byte_clk0", "pll_dsi_clk0",
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"pll_byte_clk1", "pll_dsi_clk1",
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"mdp_core_clk", "esync_clk_rcg";
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vddio-supply = <&L12B>;
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vci-supply = <&L13B>;
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vdd-supply = <&L11B>;
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tvdd-supply = <&L4B>;
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};
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&sde_dsi1 {
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clocks = <&mdss_dsi_phy0 0>,
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<&mdss_dsi_phy0 1>,
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<&mdss_dsi_phy1 0>,
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<&mdss_dsi_phy1 1>,
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/*
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* Currently the dsi clock handles are under the dsi
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* controller DT node. As soon as the controller probe
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* finishes, the dispcc sync state can get called before
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* the dsi_display probe potentially disturbing the clock
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* votes for cont_splash use case. Hence we are no longer
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* protected by the component model in this case against the
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* disp cc sync state getting triggered after the dsi_ctrl
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* probe. To protect against this incorrect sync state trigger
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* add this dummy MDP clk vote handle to the dsi_display
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* DT node. Since the dsi_display driver does not parse
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* MDP clock nodes, no actual vote shall be added and this
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* change is done just to satisfy sync state requirements.
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*/
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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/*
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* The esync clk RCG is only necessary here to set its parent
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* to the pll dsi clk, which also needs to be available at the
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* point that its known whether the clock will be used. After
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* updating the parent, this clock handle is no longer needed.
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*/
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<&dispcc DISP_CC_ESYNC1_CLK_SRC>;
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clock-names = "pll_byte_clk0", "pll_dsi_clk0",
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"pll_byte_clk1", "pll_dsi_clk1",
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"mdp_core_clk", "esync_clk_rcg";
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vddio-supply = <&L12B>;
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vci-supply = <&L13B>;
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vdd-supply = <&L11B>;
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tvdd-supply = <&L4B>;
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};
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&mdss_mdp {
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connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2
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&sde_dp &sde_cesta>;
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};
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&dsi_vtdr6130_amoled_cmd {
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qcom,ulps-enabled;
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
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};
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timing@1 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
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};
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timing@2 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
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};
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timing@3 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
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};
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};
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};
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&dsi_vtdr6130_amoled_qsync_144hz_cmd {
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qcom,ulps-enabled;
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};
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&dsi_nt37801_amoled_cmd {
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
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};
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timing@1 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
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};
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timing@2 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
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};
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timing@3 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
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};
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timing@4 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
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};
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};
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};
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&dsi_nt37801_amoled_cmd_cphy {
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
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};
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timing@1 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
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};
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timing@2 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
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};
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};
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};
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&dsi_nt37801_amoled_fhd_plus_cmd {
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
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};
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timing@1 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
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};
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timing@2 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
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};
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timing@3 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
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};
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timing@4 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
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};
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};
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};
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&dsi_nt37801_amoled_cmd_spr {
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
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};
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};
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};
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&dsi_sharp_4k_dsc_cmd {
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qcom,ulps-enabled;
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};
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&dsi_sim_cmd {
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qcom,ulps-enabled;
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qcom,mdss-dsi-display-timings {
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timing@0 { /* WQHD 60FPS cmd vid mode*/
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qcom,panel-roi-alignment = <720 40 720 40 720 40>;
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qcom,partial-update-enabled = "single_roi";
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};
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timing@2 { /* FHD 60FPS cmd mode*/
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qcom,panel-roi-alignment = <540 20 540 20 540 20>;
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qcom,partial-update-enabled = "single_roi";
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};
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timing@3 { /* HD 60FPS cmd mode*/
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qcom,panel-roi-alignment = <360 40 360 40 360 40>;
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qcom,partial-update-enabled = "single_roi";
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};
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};
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};
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&dsi_sim_dsc_375_cmd {
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qcom,ulps-enabled;
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};
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&dsi_sim_dsc_10b_cmd {
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qcom,ulps-enabled;
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};
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&dsi_dual_sim_cmd {
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qcom,ulps-enabled;
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};
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&dsi_dual_sim_dsc_375_cmd {
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qcom,ulps-enabled;
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};
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&dsi_sim_sec_hd_cmd {
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qcom,ulps-enabled;
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,panel-roi-alignment = <720 40 720 40 720 40>;
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qcom,partial-update-enabled = "single_roi";
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};
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};
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};
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