android_kernel_samsung_sm8750-devicetrees/display/kera-sde-display.dtsi

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,dispcc-tuna.h>
#include "kera-sde-display-common.dtsi"

&soc {
	sde_wb2: qcom,wb-display@2 {
		compatible = "qcom,wb-display";
		cell-index = <0>;
		label = "wb_display2";
		clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
		clock-names = "mdp_core_clk";
	};
};

&sde_dsi {
	clocks = <&mdss_dsi_phy0 0>,
		 <&mdss_dsi_phy0 1>,
		 <&mdss_dsi_phy1 0>,
		 <&mdss_dsi_phy1 1>,
		 /*
		  * Currently the dsi clock handles are under the dsi
		  * controller DT node. As soon as the controller probe
		  * finishes, the dispcc sync state can get called before
		  * the dsi_display probe potentially disturbing the clock
		  * votes for cont_splash use case. Hence we are no longer
		  * protected by the component model in this case against the
		  * disp cc sync state getting triggered after the dsi_ctrl
		  * probe. To protect against this incorrect sync state trigger
		  * add this dummy MDP clk vote handle to the dsi_display
		  * DT node. Since the dsi_display driver does not parse
		  * MDP clock nodes, no actual vote shall be added and this
		  * change is done just to satisfy sync state requirements.
		  */
		 <&dispcc DISP_CC_MDSS_MDP_CLK>;
	clock-names = "pll_byte_clk0", "pll_dsi_clk0",
		      "pll_byte_clk1", "pll_dsi_clk1",
		      "mdp_core_clk";

	vddio-supply = <&L8B>;
	vci-supply = <&L19B>;
	vdd-supply = <&L1G>;
};

&sde_dsi1 {
	clocks = <&mdss_dsi_phy0 0>,
		 <&mdss_dsi_phy0 1>,
		 <&mdss_dsi_phy1 0>,
		 <&mdss_dsi_phy1 1>,
		 /*
		  * Currently the dsi clock handles are under the dsi
		  * controller DT node. As soon as the controller probe
		  * finishes, the dispcc sync state can get called before
		  * the dsi_display probe potentially disturbing the clock
		  * votes for cont_splash use case. Hence we are no longer
		  * protected by the component model in this case against the
		  * disp cc sync state getting triggered after the dsi_ctrl
		  * probe. To protect against this incorrect sync state trigger
		  * add this dummy MDP clk vote handle to the dsi_display
		  * DT node. Since the dsi_display driver does not parse
		  * MDP clock nodes, no actual vote shall be added and this
		  * change is done just to satisfy sync state requirements.
		  */
		 <&dispcc DISP_CC_MDSS_MDP_CLK>;
	clock-names = "pll_byte_clk0", "pll_dsi_clk0",
		      "pll_byte_clk1", "pll_dsi_clk1",
		      "mdp_core_clk";

	vddio-supply = <&L8B>;
	vci-supply = <&L19B>;
	vdd-supply = <&L1G>;
};

&mdss_mdp {
	connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2 &sde_dp>;
};

&dsi_vtdr6130_amoled_cmd {
	qcom,ulps-enabled;
	qcom,mdss-dsi-display-timings {
		timing@0 {
			qcom,partial-update-enabled = "single_roi";
			qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
		};

		timing@1 {
			qcom,partial-update-enabled = "single_roi";
			qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
		};

		timing@2 {
			qcom,partial-update-enabled = "single_roi";
			qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
		};

		timing@3 {
			qcom,partial-update-enabled = "single_roi";
			qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
		};
	};
};

&dsi_vtdr6130_amoled_qsync_144hz_cmd {
	qcom,ulps-enabled;
};

&dsi_sim_cmd {
	qcom,ulps-enabled;
	qcom,mdss-dsi-display-timings {
		timing@0 { /* WQHD 60FPS cmd vid mode*/
			qcom,panel-roi-alignment = <720 40 720 40 720 40>;
			qcom,partial-update-enabled = "single_roi";
		};

		timing@2 { /* FHD 60FPS cmd mode*/
			qcom,panel-roi-alignment = <540 20 540 20 540 20>;
			qcom,partial-update-enabled = "single_roi";
		};

		timing@3 { /* HD 60FPS cmd mode*/
			qcom,panel-roi-alignment = <360 40 360 40 360 40>;
			qcom,partial-update-enabled = "single_roi";
		};
	};
};

&dsi_sim_dsc_375_cmd {
	qcom,ulps-enabled;
};

&dsi_sim_dsc_10b_cmd {
	qcom,ulps-enabled;
};

&dsi_dual_sim_cmd {
	qcom,ulps-enabled;
};

&dsi_dual_sim_dsc_375_cmd {
	qcom,ulps-enabled;
};

&dsi_sim_sec_hd_cmd {
	qcom,ulps-enabled;
	qcom,mdss-dsi-display-timings {
		timing@0 {
			qcom,panel-roi-alignment = <720 40 720 40 720 40>;
			qcom,partial-update-enabled = "single_roi";
		};
	};
};