ac218ced98
Currently, wait_for_device_probe api added before dwc3_probe is called in core_init which is suppose to ensure that in case the child is getting teared down, the userspace doesn't get to write UDC and do gadget_start. However, wait_for_device_probe api makes sure that the driver wait until all probes are completed. Ideally, it wouldn't be a problem but in cases of other driver's probe fails, usb would be affected here even though usb isn't at fault. Fix this by making a dummy-dependency on smmu node since the original intention of the patch was to make sure if smmu driver was probed successfully, then only proceed for child driver's probe. Change-Id: Id05797f8dcd26783e3c0eab4facf4f4672790fe6 Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com> Signed-off-by: Ke Du <quic_kedu@quicinc.com>
117 lines
3.1 KiB
Plaintext
117 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,gcc-monaco.h>
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#include <dt-bindings/interconnect/qcom,monaco.h>
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&soc {
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/* Primary USB port related controller */
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usb0: hsusb@4e00000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x4e00000 0x100000>;
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reg-names = "core_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event_irq", "hs_phy_irq";
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clocks = <&gcc GCC_USB20_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
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<&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>,
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<&gcc GCC_USB2_PRIM_CLKREF_CLK>,
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<&gcc GCC_USB20_SLEEP_CLK>,
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<&gcc GCC_USB20_MOCK_UTMI_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"xo", "sleep_clk", "utmi_clk";
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resets = <&gcc GCC_USB20_PRIM_BCR>;
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reset-names = "core_reset";
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USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>;
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dpdm-supply = <&usb2_phy0>;
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extcon = <&eud>;
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qcom,core-clk-rate = <60000000>;
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qcom,default-bus-vote = <2>; /* use svs bus voting */
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interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
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interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
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<&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>;
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qcom,pm-qos-latency = <2>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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/*
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* Establish dependency on smmu driver so that depopulate path of
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* deferred probe doesn't run into existing bug in smmu driver.
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*/
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dummy-supply = <&apps_smmu>;
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dwc3@4e00000 {
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compatible = "snps,dwc3";
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reg = <0x4e00000 0xcd00>;
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iommus = <&apps_smmu 0x120 0x0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>;
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interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
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snps,disable-clk-gating;
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snps,is-utmi-l1-suspend;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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maximum-speed = "high-speed";
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dr_mode = "otg";
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};
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};
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/* Primary USB port related High Speed PHY */
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usb2_phy0: hsphy@1613000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x1613000 0x120>,
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<0x01612000 0x4>;
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reg-names = "hsusb_phy_base",
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"eud_enable_reg";
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vdd-supply = <&L12A>;
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vdda18-supply = <&L14A>;
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vdda33-supply = <&L25A>;
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qcom,vdd-voltage-level = <0 904000 904000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
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clock-names = "ref_clk_src";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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qcom,param-override-seq =
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<0x63 0x6c /* override_x0 */
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0xC8 0x70 /* override_x1 */
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0x17 0x74>; /* override x2 */
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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};
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