b95184acc2
From Pakala, clock driver moved the GDSC from regulator framework to GenPd to match with upstream. Add support to use GenPD using pm_runtime apis on Kera. Signed-off-by: Aishanya Srivastava<quic_aishanya@quicinc.com> Change-Id: Id4be9a5cd189b7c427663c3d1322fbcdb8549d37
129 lines
3.7 KiB
Plaintext
129 lines
3.7 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&soc {
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msm_vidc: qcom,vidc@aa00000 {
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compatible = "qcom,kera-vidc";
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status = "okay";
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/* IOMMU Config */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0aa00000 0xF0000>;
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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/* Power Domains */
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power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
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<&videocc VIDEO_CC_MVS0_GDSC>;
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power-domain-names = "iris-ctl", "vcodec";
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/* Clocks */
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clocks =
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<&gcc GCC_VIDEO_AXI0_CLK>,
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<&videocc VIDEO_CC_MVS0C_CLK>,
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<&videocc VIDEO_CC_MVS0_CLK>,
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<&videocc VIDEO_CC_MVS0_CLK_SRC>;
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clock-names =
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"gcc_video_axi0_clk",
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"video_cc_mvs0c_clk",
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"video_cc_mvs0_clk",
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"video_cc_mvs0_clk_src";
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/* Bus Interconnects */
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interconnects =
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>,
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<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
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<&mmss_noc MASTER_VIDEO_MVP &gem_noc SLAVE_LLCC>;
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interconnect-names =
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"venus-cnoc",
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"venus-ddr",
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"venus-llcc";
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/* FW load region */
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memory-region = <&video_mem>;
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/* Clock Resets */
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resets =
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<&gcc GCC_VIDEO_AXI0_CLK_ARES>,
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<&videocc VIDEO_CC_XO_CLK_ARES>,
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<&videocc VIDEO_CC_MVS0C_CLK_ARES>,
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<&videocc VIDEO_CC_MVS0_CLK_ARES>;
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reset-names =
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"video_axi_reset",
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"video_xo_reset",
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"video_mvs0c_reset",
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"video_mvs0_reset";
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/* MMUs */
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iommu_region_partition: iommu_region_partition {
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/* These IOVA regions are unique per context bank */
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iommu-addresses = <&non_secure_pixel_cb 0x0 0x00100000>,
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<&non_secure_pixel_cb 0xe0000000 0x20000000>,
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<&non_secure_cb 0x0 0x25800000>,
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<&non_secure_cb 0xe0000000 0x20000000>,
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<&secure_non_pixel_cb 0x0 0x01000000>,
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<&secure_non_pixel_cb 0x25800000 0xda800000>,
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<&secure_bitstream_cb 0x0 0x00500000>,
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<&secure_bitstream_cb 0xe0000000 0x20000000>,
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<&secure_pixel_cb 0x0 0x00500000>,
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<&secure_pixel_cb 0xe0000000 0x20000000>;
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};
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non_secure_pixel_cb: non_secure_pixel_cb {
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compatible = "qcom,vidc,cb-ns-pxl";
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iommus = <&apps_smmu 0x1947 0x0000>;
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memory-region = <&iommu_region_partition>;
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qcom,iommu-faults = "non-fatal";
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qcom,iova-best-fit;
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/* log2 of desired alignment (1MB) - log2 of PAGE_SIZE; (8 = 20 - 12) */
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qcom,iova-max-align-shift = <8>;
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dma-coherent;
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};
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non_secure_cb: non_secure_cb {
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compatible = "qcom,vidc,cb-ns";
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iommus = <&apps_smmu 0x1940 0x0000>;
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memory-region = <&iommu_region_partition>;
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qcom,iommu-faults = "non-fatal";
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qcom,iova-best-fit;
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qcom,iova-max-align-shift = <8>; /* 1 MB */
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dma-coherent;
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};
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secure_non_pixel_cb: secure_non_pixel_cb {
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compatible = "qcom,vidc,cb-sec-non-pxl";
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iommus = <&apps_smmu 0x1944 0x0000>;
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memory-region = <&iommu_region_partition>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */
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qcom,iova-best-fit;
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qcom,iova-max-align-shift = <8>; /* 1 MB */
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qcom,secure-context-bank;
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};
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secure_bitstream_cb: secure_bitstream_cb {
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compatible = "qcom,vidc,cb-sec-bitstream";
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iommus = <&apps_smmu 0x1941 0x0004>;
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memory-region = <&iommu_region_partition>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
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qcom,iova-best-fit;
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qcom,iova-max-align-shift = <8>; /* 1 MB */
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qcom,secure-context-bank;
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};
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secure_pixel_cb: secure_pixel_cb {
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compatible = "qcom,vidc,cb-sec-pxl";
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iommus = <&apps_smmu 0x1943 0x0000>;
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memory-region = <&iommu_region_partition>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
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qcom,iova-best-fit;
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qcom,iova-max-align-shift = <8>; /* 1 MB */
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qcom,secure-context-bank;
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};
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};
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};
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