android_kernel_samsung_sm8750-devicetrees/volcano6i-peach-cnss.dtsi

// SPDX-License-Identifier: BSD-3-Clause

/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/interconnect/qcom,volcano.h>

&tlmm {
	cnss_pins {
		cnss_wlan_en_active: cnss_wlan_en_active {
			mux {
				pins = "gpio44";
				function = "gpio";
			};

			config {
				pins = "gpio44";
				drive-strength = <16>;
				output-high;
				bias-pull-up;
			};
		};

		cnss_wlan_en_sleep: cnss_wlan_en_sleep {
			mux {
				pins = "gpio44";
				function = "gpio";
			};

			config {
				pins = "gpio44";
				drive-strength = <2>;
				output-low;
				bias-pull-down;
			};
		};

		cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
			mux {
				pins = "gpio45";
				function = "wcn_sw_ctrl";

			};
		};

		cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
			mux {
				pins = "gpio52";
				function = "wcn_sw";
			};
		};
	};
};

&reserved_memory {
	cnss_wlan_mem: cnss_wlan_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x2000000>;
	};
};

&soc {
	wlan_peach: qcom,cnss-peach@b0000000 {
		compatible = "qcom,cnss-peach";
		reg = <0xb0000000 0x10000>;
		reg-names = "smmu_iova_ipa";
		qcom,wlan-sw-ctrl-gpio = <&tlmm 52 0>;

		supported-ids = <0x110E>;
		wlan-en-gpio = <&tlmm 44 0>;
		qcom,sw-ctrl-gpio = <&tlmm 45 0>;
		/* List of GPIOs to be setup for interrupt wakeup capable */
		mpm_wake_set_gpios = <45 52>;
		pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
				"sw_ctrl_wl_cx";
		pinctrl-0 = <&cnss_wlan_en_active>;
		pinctrl-1 = <&cnss_wlan_en_sleep>;
		pinctrl-2 = <&cnss_wlan_sw_ctrl>;
		pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
		qcom,wlan;
		qcom,wlan-rc-num = <0>;
		qcom,wlan-ramdump-dynamic = <0x780000>;
		cnss-enable-self-recovery;
		qcom,wlan-cbc-enabled;
		use-pm-domain;
		qcom,same-dt-multi-dev;
		/* For AOP communication, use direct QMP instead of mailbox */
		qcom,qmp = <&aoss_qmp>;

		vdd-wlan-io-supply = <&L1B>;
		qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
		vdd-wlan-io12-supply = <&L5B>;
		qcom,vdd-wlan-io12-config = <1200000 1200000 0 0 1>;
		vdd-wlan-aon-supply = <&S1K>;
		qcom,vdd-wlan-aon-config = <876000 1004000 0 0 0>;
		vdd-wlan-dig-supply = <&S1L>;
		qcom,vdd-wlan-dig-config = <876000 1000000 0 0 0>;
		vdd-wlan-rfa1-supply = <&S1B>;
		qcom,vdd-wlan-rfa1-config = <1860000 2000000 0 0 1>;
		vdd-wlan-rfa2-supply = <&S2B>;
		qcom,vdd-wlan-rfa2-config = <1312000 1340000 0 0 1>;
		vdd-wlan-ant-share-supply = <&L18B>;
		qcom,vdd-wlan-ant-share-config = <2800000 2800000 0 0 1>;

		interconnects =
		<&pcie_anoc MASTER_PCIE_0 &pcie_anoc SLAVE_ANOC_PCIE_GEM_NOC>,
		<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
		interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";

		qcom,icc-path-count = <2>;
		qcom,bus-bw-cfg-count = <9>;
		qcom,bus-bw-cfg =
		/** ICC Path 1 **/
		<0 0>, /* no vote */
		/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
		<2250 800000>,
		/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
		<7500 800000>,
		/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
		<30000 800000>,
		/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
		<100000 800000>,
		/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
		<175000 3224000>,
		/* ultra high: DBS mode snoc/anoc: 403 Mhz */
		<312500 3224000>,
		/* super high: DBS mode snoc/anoc: 533 Mhz */
		<587500 4264000>,
		/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
		<7500 1600000>,

		/** ICC Path 2 **/
		<0 0>,
		/* idle: 0-18 Mbps ddr: 547.2 MHz */
		<2250 2188800>,
		/* low: 18-60 Mbps ddr: 547.2 MHz */
		<7500 2188800>,
		/* medium: 60-240 Mbps ddr: 547.2 MHz */
		<30000 2188800>,
		/* high: 240-1200 Mbps ddr: 547.2 MHz */
		<100000 2188800>,
		/* very high: > 1200 Mbps ddr: 1555 MHz */
		<175000 6220800>,
		/* ultra high: DBS mode ddr: 2092 MHz */
		<312500 8368000>,
		/* super high: DBS mode ddr: 3.2 GHz */
		<587500 12800000>,
		/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
		<7500 2188800>;

		qcom,pdc_init_table =
			"{class: wlan_pdc, ss: rf, res: s2b.v, dwnval: 1244}",
			"{class: wlan_pdc, ss: rf, res: s3b.v, enable: 0}",
			"{class: wlan_pdc, ss: rf, res: l5b.m, enable: 1}",
			"{class: wlan_pdc, ss: rf, res: g1f.e, enable: 0}",
			"{class: wlan_pdc, ss: rf, res: l1b.m, enable: 1}",
			"{class: wlan_pdc, ss: rf, res: s3b.m, enable: 0}",
			"{class: wlan_pdc, ss: bb, res: pdc, enable: 1}";
	};
};

&wpss_pas {
	status = "disabled";
};

&wpss_mem {
	status = "disabled";
};

&pcie0_rp {
	#address-cells = <5>;
	#size-cells = <0>;

	cnss_pci0: cnss_pci0 {
		reg = <0 0 0 0 0>;
		qcom,iommu-group = <&cnss_pci_iommu_group0>;
		memory-region = <&cnss_wlan_mem>;

		#address-cells = <1>;
		#size-cells = <1>;

		cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
			qcom,iommu-msi-size = <0x1000>;
			qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
			qcom,iommu-geometry = <0xa0000000 0x10010000>;
			qcom,iommu-dma = "fastmap";
			qcom,iommu-pagetable = "coherent";
			qcom,iommu-faults = "stall-disable", "HUPCF",
				"non-fatal";
		};
	};
};