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android_kernel_samsung_sm87…/kera-audio-overlay.dtsi
Ravulapati Vishnu Vardhan Rao 78c03916fe ARM: dts: msm: update clk div factor entry for TX and VA macros 
Update clk div factor entries for TX and VA macros to reflect
proper HW configuration.

Change-Id: Ic5456d7e30245a484b6a4888835c7e6f838eb92b
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
2025-02-25 19:50:30 +05:30

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <bindings/qcom,audio-ext-clk.h>
#include <bindings/qcom,lpass-cdc-clk-rsc.h>
#include <bindings/audio-codec-port-types.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "kera-lpi.dtsi"
&lpass_cdc {
qcom,num-macros = <4>;
qcom,lpass-cdc-version = <7>;
#address-cells = <1>;
#size-cells = <1>;
lpass-cdc-clk-rsc-mngr {
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>,
<0x3004 0x3 0x1>, <0x3080 0x2 0x2>;
qcom,rx_mclk_mode_muxsel = <0x06BEC0D8>;
qcom,wsa_mclk_mode_muxsel = <0x06BEA110>;
clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk",
"rx_tx_core_clk", "wsa_tx_core_clk", "va_core_clk";
clocks = <&clock_audio_tx_1 0>, <&clock_audio_rx_1 0>,
<&clock_audio_wsa_1 0>, <&clock_audio_rx_tx 0>,
<&clock_audio_wsa_tx 0>, <&clock_audio_va_1 0>;
};
va_macro: va-macro@7660000 {
compatible = "qcom,lpass-cdc-va-macro";
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
qcom,va-clk-mux-select = <1>;
/*
* Clk divding factors for each DMIC pair.
* Valid entries for each DMIC pair:
* 2, 3, 4, 6, 8, 16
*
* These factors are translated to corresponding config values
* for the following registers,
* -- LPASS_VA_TOP_CSR_DMIC0_CTL,
* -- LPASS_VA_TOP_CSR_DMIC1_CTL,
* -- LPASS_VA_TOP_CSR_DMIC2_CTL,
* -- LPASS_VA_TOP_CSR_DMIC3_CTL,
*/
qcom,va-dmic-clk-div-factor = <16 16 16 16>;
qcom,default-clk-id = <TX_CORE_CLK>;
qcom,use-clk-id = <VA_CORE_CLK>;
qcom,is-used-swr-gpio = <1>;
qcom,va-swr-gpios = <&va_swr_gpios>;
swr2: va_swr_master {
compatible = "qcom,swr-mstr";
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_core_hw_vote",
"lpass_audio_hw_vote";
clocks = <&lpass_core_hw_vote 0>,
<&lpass_audio_hw_vote 0>;
qcom,swr_master_id = <3>;
qcom,mipi-sdw-block-packing-mode = <1>;
interrupts =
<GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "swr_master_irq", "swr_wake_irq";
qcom,swr-wakeup-required = <1>;
qcom,swr-num-ports = <5>;
qcom,swr-port-mapping = <1 SWRM_TX_PCM_OUT 0x3>,
<2 SWRM_TX1_CH1 0x1>, <2 SWRM_TX1_CH2 0x2>,
<2 SWRM_TX1_CH3 0x4>, <2 SWRM_TX1_CH4 0x8>,
<3 SWRM_TX2_CH1 0x1>, <3 SWRM_TX2_CH2 0x2>,
<3 SWRM_TX2_CH3 0x4>, <3 SWRM_TX2_CH4 0x8>,
<4 SWRM_TX3_CH1 0x1>, <4 SWRM_TX3_CH2 0x2>,
<4 SWRM_TX3_CH3 0x4>, <4 SWRM_TX3_CH4 0x8>,
<5 SWRM_TX_PCM_IN 0x3>;
qcom,swr-num-dev = <5>;
qcom,swr-clock-stop-mode0 = <1>;
qcom,swr-mstr-irq-wakeup-capable = <1>;
qcom,is-always-on = <1>;
wcd9378_tx_slave: wcd9378-tx-slave {
compatible = "qcom,wcd9378-slave";
reg = <0x10 0x01170223>;
};
wcd939x_tx_slave: wcd939x-tx-slave {
status = "disabled";
compatible = "qcom,wcd939x-slave";
reg = <0x0E 0x01170223>;
};
};
};
tx_macro: tx-macro@6AE0000 {
compatible = "qcom,lpass-cdc-tx-macro";
qcom,default-clk-id = <TX_CORE_CLK>;
/*
* Clk divding factors for each DMIC pair.
* Valid entries for each DMIC pair:
* 2, 3, 4, 6, 8, 16
*
* These factors are translated to corresponding config values
* for the following registers,
* -- LPASS_VA_TOP_CSR_DMIC0_CTL,
* -- LPASS_VA_TOP_CSR_DMIC1_CTL,
* -- LPASS_VA_TOP_CSR_DMIC2_CTL,
* -- LPASS_VA_TOP_CSR_DMIC3_CTL,
*/
qcom,tx-dmic-clk-div-factor = <4 4 4 4>;
qcom,is-used-swr-gpio = <0>;
};
rx_macro: rx-macro@6AC0000 {
compatible = "qcom,lpass-cdc-rx-macro";
qcom,rx-swr-gpios = <&rx_swr_gpios>;
qcom,rx_mclk_mode_muxsel = <0x06BEC0D8>;
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
qcom,default-clk-id = <RX_TX_CORE_CLK>;
clock-names = "rx_mclk2_2x_clk";
clocks = <&clock_audio_rx_mclk2_2x_clk 0>;
swr1: rx_swr_master {
compatible = "qcom,swr-mstr";
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_core_hw_vote",
"lpass_audio_hw_vote";
clocks = <&lpass_core_hw_vote 0>,
<&lpass_audio_hw_vote 0>;
qcom,swr_master_id = <2>;
qcom,mipi-sdw-block-packing-mode = <1>;
interrupt-names = "swr_master_irq";
qcom,swr-num-ports = <12>;
qcom,swr-port-mapping = <1 HPH_L 0x1>,
<1 HPH_R 0x2>, <2 CLSH 0x3>,
<3 COMP_L 0x1>, <3 COMP_R 0x2>,
<4 LO 0x1>, <5 DSD_L 0x1>,
<5 DSD_R 0x2>, <6 PCM_OUT1 0x01>,
<7 GPPO 0x03>, <8 HAPT 0x03>,
<9 HIFI_PCM_L 0x01>, <9 HIFI_PCM_R 0x2>,
<10 HPTH 0x03>, <11 CMPT 0x03>, <12 IPCM 0x03>;
/* num-dev is 2 if WCD RX and PMIC SWR Slaves are connected */
/* num-dev is 1 if only WCD RX slave is connected */
qcom,swr-num-dev = <1>;
qcom,swr-clock-stop-mode0 = <1>;
swr_haptics: swr_haptics@f0170220 {
compatible = "qcom,pmih010x-swr-haptics";
reg = <0x03 0xf0170220>;
//swr-slave-supply = <&hap_swr_slave_reg>;
qcom,rx_swr_ch_map = <0 0x01 0x01 0 PCM_OUT1>;
status = "disabled";
};
wcd9378_rx_slave: wcd9378-rx-slave {
compatible = "qcom,wcd9378-slave";
reg = <0x10 0x01170224>;
status = "okay";
};
wcd939x_rx_slave: wcd939x-rx-slave {
compatible = "qcom,wcd939x-slave";
reg = <0x0E 0x01170224>;
status = "disabled";
};
};
};
wsa_macro: wsa-macro@6B00000 {
compatible = "qcom,lpass-cdc-wsa-macro";
wsa_data_fs_ctl_reg = <0x6B6F000>;
qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
qcom,wsa-bat-cfgs= <1>, <1>;
qcom,wsa-rloads= <2>, <2>;
qcom,wsa-system-gains= <0 9>, <0 9>;
qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
qcom,default-clk-id = <WSA_TX_CORE_CLK>;
qcom,thermal-max-state = <11>;
qcom,noise-gate-mode = <2>;
#cooling-cells = <2>;
swr0: wsa_swr_master {
compatible = "qcom,swr-mstr";
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_core_hw_vote",
"lpass_audio_hw_vote";
clocks = <&lpass_core_hw_vote 0>,
<&lpass_audio_hw_vote 0>;
qcom,swr_master_id = <1>;
qcom,mipi-sdw-block-packing-mode = <0>;
interrupt-names = "swr_master_irq";
qcom,swr-num-ports = <13>;
qcom,swr-clock-stop-mode0 = <1>;
qcom,swr-port-mapping = <1 SPKR_L 0x1>,
<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
<6 SPKR_R_BOOST 0x3>, <7 PBR 0x3>,
<8 SPKR_HAPT 0x3>, <9 OCPM 0x3>,
<10 SPKR_L_VI 0x3>, <11 SPKR_R_VI 0x3>,
<12 SPKR_IPCM 0x3>, <13 CPS 0x3>;
qcom,swr-num-dev = <1>;
qcom,dynamic-port-map-supported = <0>;
wsa884x_0220: wsa884x@02170220 {
compatible = "qcom,wsa884x";
status = "disabled";
reg = <0x4 0x2170220>;
qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
qcom,lpass-cdc-handle = <&lpass_cdc>;
qcom,wsa-macro-handle = <&wsa_macro>;
qcom,swr-wsa-port-params =
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>,
<OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>,
<OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>,
<OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>,
<OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>,
<OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>,
<OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>,
<OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>,
<OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>;
cdc-vdd-1p8-supply = <&L7B>;
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
qcom,cdc-vdd-1p8-current = <20000>;
qcom,cdc-vdd-1p8-lpm-supported = <1>;
qcom,cdc-static-supplies = "cdc-vdd-1p8";
sound-name-prefix = "SpkrLeft";
};
wsa884x_0221: wsa884x@02170221 {
compatible = "qcom,wsa884x";
reg = <0x4 0x2170221>;
qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
qcom,lpass-cdc-handle = <&lpass_cdc>;
qcom,wsa-macro-handle = <&wsa_macro>;
qcom,swr-wsa-port-params =
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>,
<OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>,
<OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>,
<OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>,
<OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>,
<OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>,
<OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>,
<OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>,
<OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>;
cdc-vdd-1p8-supply = <&L7B>;
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
qcom,cdc-vdd-1p8-current = <20000>;
qcom,cdc-vdd-1p8-lpm-supported = <1>;
qcom,cdc-static-supplies = "cdc-vdd-1p8";
sound-name-prefix = "SpkrRight";
};
};
};
wcd939x_codec: wcd939x-codec {
compatible = "qcom,wcd939x-codec";
status = "disabled";
qcom,split-codec = <1>;
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
<4 DSD_R 0x2 0 DSD_R>, <5 HIFI_PCM_L 0x1 0 HIFI_PCM_L>,
<5 HIFI_PCM_R 0x2 0 HIFI_PCM_R>;
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
<0 ADC2 0x2 0 SWRM_TX1_CH2>,
<1 ADC3 0x1 0 SWRM_TX1_CH3>,
<1 ADC4 0x2 0 SWRM_TX1_CH4>,
<2 DMIC0 0x1 0 SWRM_TX2_CH1>,
<2 DMIC1 0x2 0 SWRM_TX2_CH2>,
<2 MBHC 0x4 0 SWRM_TX2_CH3>,
<2 DMIC2 0x4 0 SWRM_TX2_CH3>,
<2 DMIC3 0x8 0 SWRM_TX2_CH4>,
<3 DMIC4 0x1 0 SWRM_TX3_CH1>,
<3 DMIC5 0x2 0 SWRM_TX3_CH2>,
<3 DMIC6 0x4 0 SWRM_TX3_CH3>,
<3 DMIC7 0x8 0 SWRM_TX3_CH4>;
qcom,swr-tx-port-params =
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL0 LANE2>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;
qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
qcom,rx-slave = <&wcd939x_rx_slave>;
qcom,tx-slave = <&wcd939x_tx_slave>;
cdc-vdd-rx-supply = <&L7B>;
qcom,cdc-vdd-rx-voltage = <1800000 1800000>;
qcom,cdc-vdd-rx-current = <45000>;
qcom,cdc-vdd-rx-lpm-supported = <1>;
cdc-vdd-tx-supply = <&L7B>;
qcom,cdc-vdd-tx-voltage = <1800000 1800000>;
qcom,cdc-vdd-tx-current = <45000>;
qcom,cdc-vdd-tx-lpm-supported = <1>;
cdc-vdd-buck-supply = <&L7B>;
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
qcom,cdc-vdd-buck-current = <650000>;
qcom,cdc-vdd-buck-lpm-supported = <1>;
cdc-vdd-mic-bias-supply = <&BOB>;
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
qcom,cdc-vdd-mic-bias-current = <30000>;
cdc-vdd-px-supply = <&L3G>;
qcom,cdc-vdd-px-voltage = <1200000 1200000>;
qcom,cdc-vdd-px-current = <15000>;
qcom,cdc-vdd-px-lpm-supported = <1>;
qcom,cdc-vdd-px-rem-supported = <1>;
qcom,cdc-micbias1-mv = <1800>;
qcom,cdc-micbias2-mv = <1800>;
qcom,cdc-micbias3-mv = <1800>;
qcom,cdc-micbias4-mv = <1800>;
qcom,cdc-static-supplies = "cdc-vdd-rx",
"cdc-vdd-tx",
"cdc-vdd-mic-bias";
qcom,cdc-on-demand-supplies = "cdc-vdd-buck",
"cdc-vdd-px";
wcd_mb1_reg: qcom,wcd-mb1-reg {
regulator-name = "wcd-mb1-reg";
};
wcd_mb2_reg: qcom,wcd-mb2-reg {
regulator-name = "wcd-mb2-reg";
};
wcd_mb3_reg: qcom,wcd-mb3-reg {
regulator-name = "wcd-mb3-reg";
};
wcd_mb4_reg: qcom,wcd-mb4-reg {
regulator-name = "wcd-mb4-reg";
};
};
wcd9378_codec: wcd9378-codec {
compatible = "qcom,wcd9378-codec";
qcom,split-codec = <1>;
qcom,wcd-mode = <1>;
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
<4 DSD_R 0x2 0 DSD_R>;
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
<1 ADC2 0x1 0 SWRM_TX1_CH2>,
<2 ADC3 0x1 0 SWRM_TX1_CH3>,
<3 DMIC0 0x4 0 SWRM_TX2_CH1>,
<3 DMIC1 0x8 0 SWRM_TX2_CH2>,
<3 MBHC 0x1 0 SWRM_TX2_CH3>,
<4 DMIC2 0x1 0 SWRM_TX2_CH3>,
<4 DMIC3 0x2 0 SWRM_TX2_CH4>,
<4 DMIC4 0x3 0 SWRM_TX3_CH1>,
<4 DMIC5 0x4 0 SWRM_TX3_CH2>;
qcom,swr-tx-port-params =
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE1>,
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>,
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;
qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
qcom,rx-slave = <&wcd9378_rx_slave>;
qcom,tx-slave = <&wcd9378_tx_slave>;
cdc-vdd-rxtx-supply = <&L7B>;
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
qcom,cdc-vdd-rxtx-current = <30000>;
qcom,cdc-vdd-rxtx-lpm-supported = <1>;
cdc-vdd-io-supply = <&L3G>;
qcom,cdc-vdd-io-voltage = <1200000 1200000>;
qcom,cdc-vdd-io-current = <20000>;
qcom,cdc-vdd-io-lpm-supported = <1>;
cdc-vdd-buck-supply = <&L7B>;
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
qcom,cdc-vdd-buck-current = <30070>;
qcom,cdc-vdd-buck-lpm-supported = <1>;
cdc-vdd-mic-bias-supply = <&BOB>;
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
qcom,cdc-vdd-mic-bias-current = <40550>;
qcom,cdc-micbias1-mv = <1800>;
qcom,cdc-micbias2-mv = <1800>;
qcom,cdc-micbias3-mv = <1800>;
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
"cdc-vdd-io";
qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
};
};
&lpass_bt_swr {
clock-names = "bt_swr_mclk_clk", "bt_swr_mclk_clk_2x",
"lpass_core_hw_vote", "lpass_audio_hw_vote";
clocks = <&clock_audio_bt_swr_mclk_clk 0>,
<&clock_audio_bt_swr_mclk_clk_2x 0>,
<&lpass_core_hw_vote 0>,
<&lpass_audio_hw_vote 0>;
qcom,bt-swr-gpios = <&bt_swr_gpios>;
};
&swr4 {
compatible = "qcom,swr-mstr";
qcom,swr_master_id = <5>;
clock-names = "lpass_core_hw_vote",
"lpass_audio_hw_vote";
clocks = <&lpass_core_hw_vote 0>,
<&lpass_audio_hw_vote 0>;
swrm-io-base = <0x06CA0000 0x0>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "swr_master_irq";
qcom,swr-num-ports = <7>;
qcom,swr-port-mapping = <1 BT_AUDIO_RX1 0x3>,
<2 BT_AUDIO_RX2 0x3>, <3 BT_AUDIO_RX3 0x3>,
<5 BT_AUDIO_TX1 0x3>, <6 BT_AUDIO_TX2 0x3>,
<7 BT_AUDIO_TX3 0x3>, <8 FM_AUDIO_TX1 0x3>;
qcom,swr-num-dev = <1>;
};
&spf_core_platform {
kera_snd: sound {
qcom,model = "kera-qrd-snd-card";
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
qcom,mi2s-tdm-is-hw-vote-needed = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
qcom,wcn-bt = <1>;
qcom,ext-disp-audio-rx = <1>;
qcom,tdm-max-slots = <8>;
qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
qcom,mi2s-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
qcom,audio-core-list = <0>, <1>;
qcom,audio-routing =
"AMIC1", "Analog Mic1",
"AMIC1", "MIC BIAS1",
"AMIC2", "Analog Mic2",
"AMIC2", "MIC BIAS2",
"AMIC3", "Analog Mic3",
"AMIC3", "MIC BIAS3",
"AMIC4", "Analog Mic4",
"AMIC4", "MIC BIAS1",
"VA AMIC1", "Analog Mic1",
"VA AMIC1", "VA MIC BIAS1",
"VA AMIC2", "Analog Mic2",
"VA AMIC2", "VA MIC BIAS2",
"VA AMIC3", "Analog Mic3",
"VA AMIC3", "VA MIC BIAS3",
"VA AMIC4", "Analog Mic4",
"VA AMIC4", "VA MIC BIAS1",
"TX DMIC0", "Digital Mic0",
"TX DMIC0", "MIC BIAS3",
"TX DMIC1", "Digital Mic1",
"TX DMIC1", "MIC BIAS3",
"TX DMIC2", "Digital Mic2",
"TX DMIC2", "MIC BIAS1",
"TX DMIC3", "Digital Mic3",
"TX DMIC3", "MIC BIAS1",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"IN3_AUX", "AUX_OUT",
"WSA SRC0_INP", "SRC0",
"WSA_TX DEC0_INP", "TX DEC0 MUX",
"WSA_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC0_INP", "TX DEC0 MUX",
"RX_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC2_INP", "TX DEC2 MUX",
"RX_TX DEC3_INP", "TX DEC3 MUX",
"SpkrLeft IN", "WSA_SPK1 OUT",
"VA SWR_INPUT", "VA_SWR_CLK",
"VA_AIF1 CAP", "VA_SWR_CLK",
"VA_AIF2 CAP", "VA_SWR_CLK",
"VA_AIF3 CAP", "VA_SWR_CLK",
"VA DMIC0", "Digital Mic0",
"VA DMIC1", "Digital Mic1",
"VA DMIC2", "Digital Mic2",
"VA DMIC3", "Digital Mic3",
"VA DMIC0", "VA MIC BIAS3",
"VA DMIC1", "VA MIC BIAS3",
"VA DMIC2", "VA MIC BIAS1",
"VA DMIC3", "VA MIC BIAS1";
asoc-codec = <&stub_codec>, <&lpass_cdc>,
<&wcd9378_codec>, <&wsa884x_0221>;
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
"wcd9378_codec", "wsa-codec2";
qcom,msm-mbhc-usbc-audio-supported = <1>;
qcom,msm-mbhc-hphl-swh = <0>;
qcom,msm-mbhc-gnd-swh = <0>;
qcom,wsa-max-devs = <1>;
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
<&lpass_cdc>, <&lpass_bt_swr>;
};
cdc_pri_mi2s_gpios: pri_mi2s_pinctrl {
status = "disabled";
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&i2s0_sck_active &i2s0_ws_active
&i2s0_sd0_active>;
pinctrl-1 = <&i2s0_sck_sleep &i2s0_ws_sleep
&i2s0_sd0_sleep>;
#gpio-cells = <0>;
};
cdc_quat_mi2s_gpios: quat_mi2s_pinctrl {
status = "disabled";
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&quat_mi2s_sck_active &quat_mi2s_ws_active
&quat_mi2s_sd0_active &quat_mi2s_sd1_active
&quat_mi2s_sd2_active &quat_mi2s_sd3_active>;
pinctrl-1 = <&quat_mi2s_sck_sleep &quat_mi2s_ws_sleep
&quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep
&quat_mi2s_sd2_sleep &quat_mi2s_sd3_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <138 143>;
#gpio-cells = <0>;
};
cdc_quin_mi2s_gpios: quin_mi2s_pinctrl {
status = "disabled";
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&lpi_i2s1_sck_active &lpi_i2s1_ws_active
&lpi_i2s1_data0_active &lpi_i2s1_data1_active>;
pinctrl-1 = <&lpi_i2s1_sck_sleep &lpi_i2s1_ws_sleep
&lpi_i2s1_data0_sleep &lpi_i2s1_data1_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <144 147>;
#gpio-cells = <0>;
};
cdc_sen_mi2s_gpios: sen_mi2s_pinctrl {
status = "disabled";
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&lpi_i2s2_sck_active &lpi_i2s2_ws_active
&lpi_i2s2_data0_active &lpi_i2s2_data1_active>;
pinctrl-1 = <&lpi_i2s2_sck_sleep &lpi_i2s2_ws_sleep
&lpi_i2s2_data0_sleep &lpi_i2s2_data1_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <148 151>;
#gpio-cells = <0>;
};
cdc_sep_mi2s_gpios: sep_mi2s_pinctrl {
status = "disabled";
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&lpi_i2s3_sck_active &lpi_i2s3_ws_active
&lpi_i2s3_data0_active &lpi_i2s3_data1_active>;
pinctrl-1 = <&lpi_i2s3_sck_sleep &lpi_i2s3_ws_sleep
&lpi_i2s3_data0_sleep &lpi_i2s3_data1_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <153 156>;
#gpio-cells = <0>;
};
wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <149>;
#gpio-cells = <0>;
};
rx_swr_gpios: rx_swr_clk_data_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
&rx_swr_data1_active>;
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
&rx_swr_data1_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <142>;
#gpio-cells = <0>;
};
va_swr_gpios: tx_swr_clk_data_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active
&tx_swr_data1_active &tx_swr_data2_active>;
pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep
&tx_swr_data1_sleep &tx_swr_data2_sleep>;
qcom,lpi-gpios;
qcom,chip-wakeup-reg = <0xf18b008>;
qcom,chip-wakeup-maskbit = <7>;
qcom,chip-wakeup-default-val = <0x1>;
qcom,tlmm-pins = <139>;
#gpio-cells = <0>;
};
cdc_dmic01_gpios: cdc_dmic01_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <144 145>;
#gpio-cells = <0>;
};
cdc_dmic23_gpios: cdc_dmic23_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <146 147>;
#gpio-cells = <0>;
};
cdc_dmic45_gpios: cdc_dmic45_pinctrl {
status = "disabled";
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <150 151>;
#gpio-cells = <0>;
};
cdc_dmic67_gpios: cdc_dmic67_pinctrl {
status = "disabled";
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>;
pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <155 156>;
#gpio-cells = <0>;
};
bt_swr_gpios: bt_swr_clk_data_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&bt_swr_clk_active &bt_swr_data_active>;
pinctrl-1 = <&bt_swr_clk_sleep &bt_swr_data_sleep>;
qcom,lpi-gpios;
#gpio-cells = <0>;
};
};
&soc {
wsa_spkr_en02: wsa_spkr_en1_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&spkr_1_sd_n_active>;
pinctrl-1 = <&spkr_1_sd_n_sleep>;
qcom,lpi-gpios;
};
wsa_spkr_en13: wsa_spkr_en2_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&spkr_2_sd_n_active>;
pinctrl-1 = <&spkr_2_sd_n_sleep>;
qcom,lpi-gpios;
};
wcd_rst_gpio: msm_cdc_pinctrl@32 {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&wcd_reset_active>;
pinctrl-1 = <&wcd_reset_sleep>;
};
clock_audio_va_1: va_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x307>;
#clock-cells = <1>;
};
clock_audio_wsa_1: wsa_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x309>;
#clock-cells = <1>;
};
clock_audio_rx_1: rx_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
qcom,codec-lpass-ext-clk-freq = <22579200>;
qcom,codec-lpass-clk-id = <0x30E>;
#clock-cells = <1>;
};
clock_audio_rx_tx: rx_core_tx_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_10>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x312>;
#clock-cells = <1>;
};
clock_audio_tx_1: tx_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x30C>;
#clock-cells = <1>;
};
clock_audio_wsa_tx: wsa_core_tx_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_11>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x314>;
#clock-cells = <1>;
};
clock_audio_rx_mclk2_2x_clk: rx_mclk2_2x_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_13>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x318>;
#clock-cells = <1>;
};
clock_audio_bt_swr_mclk_clk: bt_swr_mclk_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_15>;
qcom,codec-lpass-ext-clk-freq = <24576000>;
qcom,codec-lpass-clk-id = <0x31A>;
#clock-cells = <1>;
};
clock_audio_bt_swr_mclk_clk_2x: bt_swr_mclk_clk_2x {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_16>;
qcom,codec-lpass-ext-clk-freq = <24576000>;
qcom,codec-lpass-clk-id = <0x31B>;
#clock-cells = <1>;
};
};
&adsp_loader {
status = "ok";
};
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