165cb0eb23
Add sw fuse range to dts file for Tuna target. The swfuse_phys is only needed in primary VM. Change-Id: Ida97d23c3f0634864829ea8f7ea91e388062eb4c Signed-off-by: Sanskar Omar <quic_sansomar@quicinc.com> Signed-off-by: lnxdisplay <lnxdisplay@localhost>
472 lines
15 KiB
Plaintext
472 lines
15 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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mdss_mdp: qcom,mdss_mdp@ae00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "qcom,sde-kms";
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reg = <0x0ae00000 0x93800>,
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<0x0aeb0000 0x2008>,
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<0x0af80000 0x7000>,
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<0x400000 0x2000>,
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<0x0af50000 0x140>;
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reg-names = "mdp_phys",
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"vbif_phys",
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"regdma_phys",
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"ipcc_reg",
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"swfuse_phys";
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/* interrupt config */
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#cooling-cells = <2>;
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/* hw blocks */
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qcom,sde-off = <0x1000>;
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qcom,sde-len = <0x488>;
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qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000>;
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qcom,sde-ctl-size = <0x1000>;
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qcom,sde-ctl-display-pref = "primary", "none", "none", "none";
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qcom,sde-mixer-off = <0x45000 0x46000 0x47000
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0x48000 0x0f0f 0x0f0f
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0x0f0f 0x0f0f>;
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qcom,sde-mixer-size = <0x400>;
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qcom,sde-mixer-display-pref = "primary", "primary", "none",
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"none", "none", "none", "none", "none";
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qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none",
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"dcwb", "dcwb", "dcwb", "dcwb";
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qcom,sde-dspp-top-off = <0x1300>;
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qcom,sde-dspp-top-size = <0x8c>;
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qcom,sde-dspp-off = <0x55000 0x57000 0x59000>;
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qcom,sde-dspp-size = <0x1800>;
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qcom,sde-dspp-rc-version = <0x00010001>;
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qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800>;
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qcom,sde-dspp-rc-size = <0x100>;
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qcom,sde-dspp-rc-mem-size = <2720>;
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qcom,sde-dspp-rc-min-region-width = <20>;
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qcom,sde-dnsc-blur-version = <0x100>;
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qcom,sde-dnsc-blur-off = <0x7D000>;
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qcom,sde-dnsc-blur-size = <0x40>;
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qcom,sde-dnsc-blur-gaus-lut-off = <0x100>;
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qcom,sde-dnsc-blur-gaus-lut-size = <0x400>;
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qcom,sde-dnsc-blur-dither-off = <0x5E0>;
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qcom,sde-dnsc-blur-dither-size = <0x20>;
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qcom,sde-dest-scaler-top-off = <0x0008F000>;
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qcom,sde-dest-scaler-top-size = <0x1C>;
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qcom,sde-dest-scaler-off = <0x0 0x1000 0x2000>;
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qcom,sde-dest-scaler-size = <0x800>;
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qcom,sde-wb-off = <0x65000 0x66000>;
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qcom,sde-wb-size = <0x2c8>;
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qcom,sde-wb-xin-id = <0xa 6>;
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qcom,sde-wb-id = <1 2>;
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qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>;
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qcom,sde-intf-size = <0x4BC>;
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qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
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qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>;
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qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000
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0x67000 0x67400 0x7f000 0x7f400>;
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qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
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qcom,sde-pp-size = <0x2c>;
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qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2 0x3 0x3>;
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qcom,sde-merge-3d-off = <0x4f000 0x50000 0x67700 0x7f700>;
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qcom,sde-merge-3d-size = <0x1c>;
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qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>;
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qcom,sde-cdm-off = <0x7a200>;
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qcom,sde-cdm-size = <0x240>;
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qcom,sde-dsc-off = <0x81000 0x81000 0x82000>;
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qcom,sde-dsc-size = <0x8>;
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qcom,sde-dsc-pair-mask = <2 1 0>;
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qcom,sde-dsc-hw-rev = "dsc_1_2";
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qcom,sde-dsc-enc = <0x100 0x200 0x100>;
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qcom,sde-dsc-enc-size = <0x100>;
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qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00>;
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qcom,sde-dsc-ctl-size = <0x24>;
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qcom,sde-dsc-native422-supp = <1 1 1>;
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qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>;
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qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>;
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qcom,sde-dither-version = <0x00020000>;
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qcom,sde-dither-size = <0x20>;
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qcom,sde-sspp-type = "vig", "vig",
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"dma", "dma", "dma", "dma", "dma";
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qcom,sde-sspp-off = <0x5000 0x7000
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0x25000 0x27000 0x29000 0x2b000 0x2d000>;
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qcom,sde-sspp-src-size = <0x344>;
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qcom,sde-sspp-xin-id = <0 4 1 5 9 13 14>;
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qcom,sde-sspp-excl-rect = <1 1 1 1 1 1 1>;
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qcom,sde-sspp-smart-dma-priority = <6 7 1 2 3 4 5>;
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qcom,sde-smart-dma-rev = "smart_dma_v2p5";
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qcom,sde-mixer-pair-mask = <2 1 4 3 6 5 8 7>;
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qcom,sde-mixer-blend-op-off = <0x40 0x70 0xa0 0xd0 0x100 0x130
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0x160 0x190 0x1c0 0x1f0 0x220>;
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qcom,sde-max-per-pipe-bw-kbps = <5100000 5100000
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5100000 5100000
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5100000 5100000
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5100000>;
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qcom,sde-max-per-pipe-bw-high-kbps = <5100000 5100000
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5100000 5100000
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5100000 5100000
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5100000>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-sspp-clk-ctrl =
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<0x4330 0>, <0x6330 0>,
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<0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>,
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<0x2c330 0>;
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qcom,sde-sspp-clk-status =
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<0x4334 0>, <0x6334 0>,
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<0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>,
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<0x2c334 0>;
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qcom,sde-sspp-csc-off = <0x1a00>;
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qcom,sde-csc-type = "csc-10bit";
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qcom,sde-qseed-sw-lib-rev = "qseedv3lite";
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qcom,sde-qseed-scalar-version = <0x3004>;
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qcom,sde-sspp-qseed-off = <0xa00>;
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qcom,sde-mixer-linewidth = <2560>;
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qcom,sde-sspp-linewidth = <5120>;
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qcom,sde-wb-linewidth = <4096>;
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qcom,sde-dsc-linewidth = <2560>;
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qcom,sde-max-dest-scaler-input-linewidth = <2048>;
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qcom,sde-max-dest-scaler-output-linewidth = <2560>;
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qcom,sde-wb-linewidth-linear = <8192>;
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qcom,sde-mixer-blendstages = <0xb>;
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qcom,sde-highest-bank-bit = <0x8 0x3>;
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qcom,sde-ubwc-version = <0x50000001>;
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qcom,sde-ubwc-swizzle = <0x6>;
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qcom,sde-ubwc-bw-calc-version = <0x1>;
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qcom,sde-ubwc-static = <0x1>;
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qcom,sde-macrotile-mode = <0x1>;
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qcom,sde-smart-panel-align-mode = <0xc>;
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qcom,sde-panic-per-pipe;
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qcom,sde-has-cdp;
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qcom,sde-has-src-split;
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qcom,sde-pipe-order-version = <0x1>;
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qcom,sde-has-dim-layer;
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qcom,sde-has-dest-scaler;
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qcom,sde-max-trusted-vm-displays = <1>;
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qcom,sde-max-bw-low-kbps = <23600000>;
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qcom,sde-max-bw-high-kbps = <27800000>;
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qcom,sde-min-core-ib-kbps = <2500000>;
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qcom,sde-min-llcc-ib-kbps = <0>;
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qcom,sde-min-dram-ib-kbps = <800000>;
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qcom,sde-dram-channels = <4>;
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qcom,sde-num-nrt-paths = <0>;
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qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400>;
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qcom,sde-dspp-spr-size = <0x200>;
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qcom,sde-dspp-spr-version = <0x00020000>;
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qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600>;
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qcom,sde-dspp-demura-size = <0x150>;
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qcom,sde-dspp-demura-version = <0x00030000>;
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qcom,sde-lm-noise-off = <0x320>;
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qcom,sde-lm-noise-version = <0x00010000>;
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qcom,sde-uidle-off = <0x80000>;
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qcom,sde-uidle-size = <0x80>;
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qcom,sde-vbif-off = <0>;
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qcom,sde-vbif-size = <0x1074>;
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qcom,sde-vbif-id = <0>;
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qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
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qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>;
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qcom,sde-vbif-default-ot-rd-limit = <40>;
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qcom,sde-vbif-default-ot-wr-limit = <32>;
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qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>;
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qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>;
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qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>;
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qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>;
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qcom,sde-vbif-qos-lutdma-remap = <4 4 4 4 5 5 5 5 4 4 4 4 5 5 5 5>;
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qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>;
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qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 4 4 5 5 5 5>;
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qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>;
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qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0
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0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0 0xffff0000 0xffff0000>;
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qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001
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0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0xff 0xff>;
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qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666
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0x00112233 0x44556666 0x00112233 0x66666666
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0x0 0x0 0x0 0x0
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0x77776666 0x66666540 0x77776666 0x66666540
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0x77776541 0x0 0x77776541 0x0
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0x00112233 0x44556666 0x00112233 0x66666666
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0x00112233 0x44556666 0x00112233 0x66666666
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0x0 0x0 0x0 0x0
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0x55555544 0x33221100 0x55555544 0x33221100>;
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qcom,sde-cdp-setting = <1 1>, <1 0>;
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qcom,sde-qos-cpu-mask = <0x3>;
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qcom,sde-qos-cpu-mask-performance = <0x3>;
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qcom,sde-qos-cpu-dma-latency = <300>;
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qcom,sde-qos-cpu-irq-latency = <300>;
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qcom,sde-ipcc-protocol-id = <0x4>;
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qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
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qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-reg-dma-off = <0 0x800>;
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qcom,sde-reg-dma-id = <0 1>;
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qcom,sde-reg-dma-version = <0x00030000>;
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qcom,sde-reg-dma-trigger-off = <0x119c>;
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qcom,sde-reg-dma-xin-id = <7>;
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qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
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qcom,sde-secure-sid-mask = <0x801>;
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qcom,sde-reg-bus,vectors-KBps = <0 0>,
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<0 14000>,
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<0 140000>,
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<0 310000>;
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qcom,sde-sspp-vig-blocks {
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vcm@0 {
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cell-index = <0>;
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qcom,sde-vig-top-off = <0x700>;
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qcom,sde-vig-csc-off = <0x1a00>;
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qcom,sde-vig-qseed-off = <0xa00>;
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qcom,sde-vig-qseed-size = <0xe0>;
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qcom,sde-vig-gamut = <0x1d00 0x00060001>;
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qcom,sde-vig-igc = <0x1d00 0x00060000>;
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qcom,sde-vig-inverse-pma;
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qcom,sde-fp16-igc = <0x200 0x00010000>;
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qcom,sde-fp16-unmult = <0x200 0x00010000>;
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qcom,sde-fp16-gc = <0x200 0x00010000>;
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qcom,sde-fp16-csc = <0x200 0x00010000>;
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qcom,sde-ucsc-igc = <0x700 0x00010001>;
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qcom,sde-ucsc-unmult = <0x700 0x00010001>;
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qcom,sde-ucsc-gc = <0x700 0x00010001>;
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qcom,sde-ucsc-csc = <0x700 0x00010001>;
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qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>;
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};
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vcm@1 {
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cell-index = <1>;
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qcom,sde-fp16-igc = <0x280 0x00010000>;
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qcom,sde-fp16-unmult = <0x280 0x00010000>;
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qcom,sde-fp16-gc = <0x280 0x00010000>;
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qcom,sde-fp16-csc = <0x280 0x00010000>;
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qcom,sde-ucsc-igc = <0x1700 0x00010001>;
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qcom,sde-ucsc-unmult = <0x1700 0x00010001>;
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qcom,sde-ucsc-gc = <0x1700 0x00010001>;
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qcom,sde-ucsc-csc = <0x1700 0x00010001>;
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qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>;
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};
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};
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qcom,sde-sspp-dma-blocks {
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dgm@0 {
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cell-index = <0>;
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qcom,sde-dma-top-off = <0x700>;
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qcom,sde-fp16-igc = <0x200 0x00010000>;
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qcom,sde-fp16-unmult = <0x200 0x00010000>;
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qcom,sde-fp16-gc = <0x200 0x00010000>;
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qcom,sde-fp16-csc = <0x200 0x00010000>;
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qcom,sde-ucsc-igc = <0x700 0x00010001>;
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qcom,sde-ucsc-unmult = <0x700 0x00010001>;
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qcom,sde-ucsc-gc = <0x700 0x00010001>;
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qcom,sde-ucsc-csc = <0x700 0x00010001>;
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qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>;
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};
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dgm@1 {
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cell-index = <1>;
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qcom,sde-fp16-igc = <0x200 0x00010000>;
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qcom,sde-fp16-unmult = <0x200 0x00010000>;
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qcom,sde-fp16-gc = <0x200 0x00010000>;
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qcom,sde-fp16-csc = <0x200 0x00010000>;
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qcom,sde-ucsc-igc = <0x1700 0x00010001>;
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qcom,sde-ucsc-unmult = <0x1700 0x00010001>;
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qcom,sde-ucsc-gc = <0x1700 0x00010001>;
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qcom,sde-ucsc-csc = <0x1700 0x00010001>;
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qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>;
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};
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};
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qcom,sde-dspp-blocks {
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qcom,sde-dspp-igc = <0x1260 0x00050000>;
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qcom,sde-dspp-hsic = <0x800 0x00010007>;
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qcom,sde-dspp-memcolor = <0x880 0x00010007>;
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qcom,sde-dspp-hist = <0x800 0x00010007>;
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qcom,sde-dspp-sixzone = <0x900 0x00020000>;
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qcom,sde-dspp-vlut = <0xa00 0x00010008>;
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qcom,sde-dspp-gamut = <0x1000 0x00040003>;
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qcom,sde-dspp-pcc = <0x1700 0x00060000>;
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qcom,sde-dspp-gc = <0x17c0 0x00020000>;
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qcom,sde-dspp-dither = <0x82c 0x00010007>;
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};
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};
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mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
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compatible = "qcom,dsi-ctrl-hw-v2.9";
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label = "dsi-ctrl-0";
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cell-index = <0>;
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frame-threshold-time-us = <800>;
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reg = <0xae94000 0x1000>,
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<0xaf0f000 0x4>,
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<0x0ae36000 0x300>;
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reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <4 0>;
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1200000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <16600>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
|
|
compatible = "qcom,dsi-ctrl-hw-v2.9";
|
|
label = "dsi-ctrl-1";
|
|
cell-index = <1>;
|
|
frame-threshold-time-us = <800>;
|
|
reg = <0xae96000 0x1000>,
|
|
<0xaf0f000 0x4>,
|
|
<0x0ae37000 0x300>;
|
|
reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <5 0>;
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1200000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <16600>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 {
|
|
compatible = "qcom,dsi-phy-v5.2";
|
|
label = "dsi-phy-0";
|
|
cell-index = <0>;
|
|
#clock-cells = <1>;
|
|
reg = <0xae95000 0xa00>,
|
|
<0xae95500 0x400>,
|
|
<0xae94200 0xa0>;
|
|
reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
|
|
pll-label = "dsi_pll_4nm";
|
|
|
|
qcom,platform-strength-ctrl = [55 03
|
|
55 03
|
|
55 03
|
|
55 03
|
|
55 00];
|
|
qcom,platform-lane-config = [00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 8a 8a];
|
|
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
|
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <950000>;
|
|
qcom,supply-enable-load = <98000>;
|
|
qcom,supply-disable-load = <96>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 {
|
|
compatible = "qcom,dsi-phy-v5.2";
|
|
label = "dsi-phy-1";
|
|
cell-index = <1>;
|
|
#clock-cells = <1>;
|
|
reg = <0xae97000 0xa00>,
|
|
<0xae97500 0x400>,
|
|
<0xae96200 0xa0>;
|
|
reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
|
|
pll-label = "dsi_pll_4nm";
|
|
|
|
qcom,platform-strength-ctrl = [55 03
|
|
55 03
|
|
55 03
|
|
55 03
|
|
55 00];
|
|
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
|
qcom,platform-lane-config = [00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 8a 8a];
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <950000>;
|
|
qcom,supply-enable-load = <98000>;
|
|
qcom,supply-disable-load = <96>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dsi_pll_codes_data:dsi_pll_codes {
|
|
reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
|
label = "dsi_pll_codes";
|
|
};
|
|
};
|