429bad87e1
Add documentation for QPIC NAND controller devicetree bindings. Change-Id: I2c5748ca639a4e42f027bfdad5873cb288090a2d Signed-off-by: Madhusudhan Sana <quic_msana@quicinc.com>
131 lines
3.0 KiB
YAML
131 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/mtd/qcom,msm-nand.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm Technologies, Inc. QPIC nand controller
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maintainers:
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- Pradeep P V K <quic_pragalla@quicinc.com>
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- Sarthak Garg <quic_sartgarg@quicinc.com>
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properties:
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compatible:
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const: qcom,msm-nand
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reg:
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maxItems: 2
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reg-names:
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maxItems: 2
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clocks:
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items:
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- description: Core Clock.
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clock-names:
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items:
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- const: core_clk
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interrupts:
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maxItems: 1
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interrupt-names:
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const: bam_irq
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iommus:
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items:
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- description: phandle to apps_smmu node with sid mask.
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qcom,iommu-dma:
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description: |
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default
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Standard iommu translation behaviour. Calling iommu and DMA apis in
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atomic context is not allowed.
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bypass
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DMA APIs will use 1-to-1 translation between dma_addr and phys_addr.
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fastmap
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DMA APIs will run faster, but use several orders of magnitude more
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memory. Also allows using iommu and DMA apis in atomic context.
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atomic
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Allows using iommu and DMA apis in atomic context.
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disabled
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The iommu client is responsible for allocating an iommu domain.
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enum:
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- default
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- bypass
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- fastmap
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- atomic
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- disabled
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dma-coherent: true
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interconnects:
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items:
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- description: data path, nand to ddr.
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interconnect-names:
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items:
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- const: nand-ddr
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qcom,reg-adjustment-offset:
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description: base adjustment offset value for the version registers.
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$ref: /schemas/types.yaml#/definitions/uint32
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nvmem-cells:
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items:
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- description: Phandle to nvmem cell that contains 'boot_config'.
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nvmem-cell-names:
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items:
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- const: boot_conf
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qcom,boot_dev_bits:
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description: Number of FAST_BOOT bits in boot_config register.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,nand_boot:
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description: boot device detection values for NAND.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,sdx75.h>
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qcom,nand@f9af0000 {
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compatible = "qcom,msm-nand";
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reg = <0xf9af0000 0x1000>,
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<0xf9ac4000 0x8000>;
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reg-names = "nand_phys",
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"bam_phys";
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qcom,reg-adjustment-offset = <0x4000>;
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interrupts = <0 279 0>;
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interrupt-names = "bam_irq";
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interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>;
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interconnect-names = "nand-ddr";
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clock-names = "core_clk";
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clocks = <&rpmhcc RPMH_QPIC_CLK>;
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nvmem-cells = <&boot_config>;
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nvmem-cell-names = "boot_conf";
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qcom,boot_dev_bits = <0x4>;
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qcom,nand_boot = <0x0>;
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iommus = <&apps_smmu 0x100 0x3>;
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qcom,iommu-dma = "atomic";
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dma-coherent;
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};
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