3c51dd18f2
git-subtree-dir: qcom/camera git-subtree-mainline:8263fe365egit-subtree-split:a1378b76f0
96 lines
2.2 KiB
Plaintext
96 lines
2.2 KiB
Plaintext
* Qualcomm Technologies, Inc. MSM camera PPI
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=======================
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Required Node Structure
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=======================
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The camera PPI node must be described in First level of device nodes. The
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first level describe the overall PPI node structure.
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======================================
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First Level Node - PPI device
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======================================
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- compatible
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Usage: required
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Value type: <string>
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Definition: Should be "qcom,ppi100".
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- cell-index: ppi hardware core index
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Usage: required
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Value type: <u32>
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Definition: Should specify the Hardware index id.
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- reg
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Usage: required
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Value type: <u32>
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Definition: offset and length of the register set
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for the device for the ppi operating in
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compatible mode.
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- reg-names
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Usage: required
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Value type: <string>
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Definition: Should specify relevant names to each
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reg property defined.
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- reg-cam-base
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Usage: required
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Value type: <string>
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Definition: offset of PPI in camera hw block
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- interrupts
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Usage: required
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Value type: <u32>
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Definition: Interrupt associated with PPI HW.
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- interrupt-names
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Usage: required
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Value type: <string>
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Definition: Name of the interrupt.
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- clock-names
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Usage: required
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Value type: <string>
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Definition: List of clock names required for PPI HW.
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- clock-rates
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Usage: required
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Value type: <u32>
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Definition: List of clock rates in Hz for PPI HW.
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- clock-cntl-level
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Usage: required
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Value type: <string>
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Definition: All different clock level node can support.
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- clocks
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Usage: required
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Value type: <phandle>
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Definition: all clock phandle and source clocks.
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- regulator-names
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Usage: required
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Value type: <string>
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Definition: name of the voltage regulators required for the device.
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- gdscr-supply
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Usage: required
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Value type: <phandle>
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Definition: should contain gdsr regulator used for PPI clocks.
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Example:
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qcom,ppi0@5cb3000 {
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cell-index = <0>;
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compatible = "qcom,ppi100";
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reg-names = "ppi0";
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reg = <0x5cb3000 0x200>;
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reg-cam-base = <0xb3000>;
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interrupt-names = "ppi0";
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interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
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clocks = <&gcc GCC_CAMSS_CPHY_0_CLK>;
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clock-names = "gcc_camss_cphy_0_clk";
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clock-cntl-level = "svs";
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clock-rates = <0>;
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status = "ok";
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};
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