3c51dd18f2
git-subtree-dir: qcom/camera git-subtree-mainline:8263fe365egit-subtree-split:a1378b76f0
378 lines
9.5 KiB
Plaintext
378 lines
9.5 KiB
Plaintext
* Qualcomm Technologies, Inc. MSM Camera ICP
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The MSM camera ICP devices are implemented multiple device nodes.
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The root icp device node has properties defined to hint the driver
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about the number of ICP, IPE and BPS nodes available during the
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probe sequence. Each node has multiple properties defined
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for interrupts, clocks and regulators. icp_v1 and icp_v2 are names
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corresponding to a5 and lx7 processors respectively.
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=======================
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Required Node Structure
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=======================
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ICP root interface node takes care of the handling account for number
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of A5, LX7, IPE and BPS devices present on the hardware.
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- compatible
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Usage: required
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Value type: <string>
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Definition: Should be "qcom,cam-icp".
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- compat-hw-name
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Usage: required
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Value type: <string>
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Definition: Should be "qcom,icp", "qcom,ipe0",
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"qcom,ipe1" or "qcom,bps".
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- num-icp
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Usage: required
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Value type: <u32>
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Definition: Number of supported icp processors. ICP can either be a5 or lx7.
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- num-ipe
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Usage: required
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Value type: <u32>
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Definition: Number of supported IPE HW blocks.
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- num-bps
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Usage: required
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Value type: <u32>
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Definition: Number of supported BPS HW blocks.
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Example:
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qcom,cam-icp {
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compatible = "qcom,cam-icp";
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compat-hw-name = "qcom,icp", "qcom,ipe0",
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"qcom,ipe0", "qcom,bps";
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num-icp = <1>;
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num-ipe = <2>;
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num-bps = <1>;
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status = "ok";
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};
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=======================
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Required Node Structure
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=======================
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A5/LX7/IPE/BPS Node's provides interface for Image Control Processor driver
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about the A5/LX7 register map, interrupt map, clocks, regulators
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and name of firmware image.
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- cell-index
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Usage: required
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Value type: <u32>
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Definition: Node instance number.
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- compatible
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Usage: required
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Value type: <string>
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Definition: Should be "qcom,cam-a5", "qcom,cam-lx7",
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"qcom,cam-ipe", "qcom,cam-ipe680", "qcom,cam-bps" or
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"qcom,cam-bps680".
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- icp-version
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Usage: required
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Value type: <u32>
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Definition: <0x0100> or <0x0200>. 0x0100 is a version tag for icp_v1 (a5).
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0x0200 is a version tag for icp_v2 (lx7). [15:8] indicates major version.
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[7:0] indicates minor version.
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- reg-names
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Usage: optional
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Value type: <string>
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Definition: Name of the register resources.
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- reg
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Usage: optional
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Value type: <u32>
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Definition: Register values.
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- reg-cam-base
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Usage: optional
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Value type: <u32>
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Definition: Register values.
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- interrupt-names
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Usage: optional
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Value type: <string>
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Definition: Name of the interrupt.
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- interrupts
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Usage: optional
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Value type: <u32>
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Definition: Interrupt associated with ICP HW.
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- regulator-names
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Usage: required
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Value type: <string>
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Definition: Name of the regulator resources for ICP HW.
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- camss-supply
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Usage: required
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Value type: <phandle>
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Definition: Regulator reference corresponding to the names listed
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in "regulator-names".
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- clock-names
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Usage: required
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Value type: <string>
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Definition: List of clock names required for ICP HW.
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- src-clock-name
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Usage: required
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Value type: <string>
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Definition: Source clock name.
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- clock-control-debugfs
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Usage: optional
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Value type: <string>
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Definition: Enable/Disable clk rate control.
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- clocks
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Usage: required
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Value type: <phandle>
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Definition: List of clocks used for ICP HW.
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- clock-cntl-level
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Usage: required
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Value type: <string>
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Definition: List of strings corresponds clock-rates levels.
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Supported strings: lowsvs, svs, svs_l1, nominal, turbo.
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- clock-rates
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Usage: required
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Value type: <u32>
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Definition: List of clocks rates.
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- fw_name
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Usage: optional
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Value type: <string>
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Definition: Name of firmware image.
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- ubwc-ipe-fetch-cfg
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Usage: required
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Value type: <u32>
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Definition: UBWC IPE fetch configuration based on DDR device type.
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- ubwc-ipe-write-cfg
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Usage: required
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Value type: <u32>
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Definition: UBWC IPE write configuration based on DDR device type.
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- ubwc-bps-fetch-cfg
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Usage: required
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Value type: <u32>
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Definition: UBWC BPS fetch configuration based on DDR device type.
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- ubwc-bps-write-cfg
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Usage: required
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Value type: <u32>
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Definition: UBWC BPS write configuration based on DDR device type.
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- ubwc-cfg
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Usage: optional
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Value type: <u32>
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Definition: UBWC configuration, this is mandatory if above
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ipe/bps ubwc properties are not used.
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- nrt-device
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Usage: optional
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Value type: <empty>
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Definition: Flag to indicate whether this is non real time device.
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- vmrm-resource-ids
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Usage: optional
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Value type: <u32>
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Definition: should specify vmrm resource id list order is mem label,
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mem tag, irq1 label, irq2 label.
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Examples:
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cam_a5: qcom,a5 {
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cell-index = <0>;
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compatible = "qcom,cam-a5";
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reg = <0xac00000 0x6000>,
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<0xac10000 0x8000>,
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<0xac18000 0x3000>;
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reg-names = "a5_qgic", "a5_sierra", "a5_csr";
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reg-cam-base = <0x00000 0x10000 0x18000>;
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interrupts = <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "a5";
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regulator-names = "camss-vdd";
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camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
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clock-names =
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"soc_fast_ahb",
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"icp_ahb_clk",
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"icp_clk_src",
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"icp_clk";
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src-clock-name = "icp_clk_src";
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clocks =
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<&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>,
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<&clock_camcc CAM_CC_ICP_AHB_CLK>,
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<&clock_camcc CAM_CC_ICP_CLK_SRC>,
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<&clock_camcc CAM_CC_ICP_CLK>;
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clock-rates =
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<0 0 400000000 0>,
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<0 0 480000000 0>,
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<0 0 600000000 0>,
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<0 0 600000000 0>,
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<0 0 600000000 0>;
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clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
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"turbo";
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nrt-device;
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fw_name = "CAMERA_ICP.elf";
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ubwc-ipe-fetch-cfg = <0x707b 0x7083>;
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ubwc-ipe-write-cfg = <0x161ef 0x1620f>;
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ubwc-bps-fetch-cfg = <0x707b 0x7083>;
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ubwc-bps-write-cfg = <0x161ef 0x1620f>;
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status = "ok";
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};
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cam_lx7: qcom,lx7 {
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cell-index = <0>;
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compatible = "qcom,cam-lx7";
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reg = <0xac01000 0x400>,
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<0xac01800 0x400>;
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reg-names = "lx7_csr", "lx7_cirq";
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reg-cam-base = <0x1000 0x1800>;
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interrupts = <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "lx7";
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regulator-names = "camss-vdd";
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camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
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clock-names =
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"soc_slow_ahb",
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"icp_ahb_clk",
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"icp_clk_src",
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"icp_clk";
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src-clock-name = "icp_clk_src";
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clocks =
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<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
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<&clock_camcc CAM_CC_ICP_AHB_CLK>,
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<&clock_camcc CAM_CC_ICP_CLK_SRC>,
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<&clock_camcc CAM_CC_ICP_CLK>;
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clock-rates =
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<80000000 0 400000000 0>,
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<80000000 0 480000000 0>,
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<80000000 0 600000000 0>,
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<80000000 0 600000000 0>,
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<80000000 0 600000000 0>;
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clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
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"turbo";
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nrt-device;
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fw_name = "CAMERA_ICP.elf";
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ubwc-ipe-fetch-cfg = <0x707b 0x7083>;
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ubwc-ipe-write-cfg = <0x161ef 0x1620f>;
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ubwc-bps-fetch-cfg = <0x707b 0x7083>;
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ubwc-bps-write-cfg = <0x161ef 0x1620f>;
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vmrm-resource-ids = <29 29 29>;
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status = "ok";
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};
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cam_ipe0: qcom,ipe0@ac42000 {
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cell-index = <0>;
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compatible = "qcom,cam-ipe", "qcom,cam-ipe680";
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reg = <0xac42000 0x18000>;
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reg-names = "ipe0_top";
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reg-cam-base = <0x42000>;
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regulator-names = "ipe0-vdd";
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ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>;
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clock-names =
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"ipe_nps_ahb_clk_src",
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"ipe_nps_ahb_clk",
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"ipe_fast_ahb_clk_src",
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"ipe_nps_fast_ahb_clk",
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"ipe_pps_fast_ahb_clk",
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"ipe_nps_clk_src",
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"ipe_nps_clk";
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"ipe_pps_clk";
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src-clock-name = "ipe_nps_clk_src";
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clock-control-debugfs = "true";
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clocks =
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<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
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<&clock_camcc CAM_CC_IPE_NPS_AHB_CLK>,
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<&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>,
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<&clock_camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>,
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<&clock_camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>,
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<&clock_camcc CAM_CC_IPE_NPS_CLK_SRC>,
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<&clock_camcc CAM_CC_IPE_NPS_CLK>,
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<&clock_camcc CAM_CC_IPE_PPS_CLK>;
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clock-rates =
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<80000000 0 100000000 0 0 364000000 0 0>,
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<80000000 0 200000000 0 0 500000000 0 0>,
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<80000000 0 300000000 0 0 600000000 0 0>,
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<80000000 0 400000000 0 0 700000000 0 0>,
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<80000000 0 400000000 0 0 700000000 0 0>;
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clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
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"turbo";
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nrt-device;
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vmrm-resource-ids = <30 30 30>;
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status = "ok";
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};
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qcom,ipe1 {
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cell-index = <1>;
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compatible = "qcom,cam-ipe";
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regulator-names = "ipe1-vdd";
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ipe1-vdd-supply = <&ipe_1_gdsc>;
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clock-names = "ipe_1_ahb_clk",
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"ipe_1_areg_clk",
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"ipe_1_axi_clk",
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"ipe_1_clk",
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"ipe_1_clk_src";
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src-clock-name = "ipe_1_clk_src";
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clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>,
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<&clock_camcc CAM_CC_IPE_1_AREG_CLK>,
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<&clock_camcc CAM_CC_IPE_1_AXI_CLK>,
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<&clock_camcc CAM_CC_IPE_1_CLK>,
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<&clock_camcc CAM_CC_IPE_1_CLK_SRC>;
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clock-rates = <0 0 0 0 240000000>,
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<0 0 0 0 404000000>,
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<0 0 0 0 480000000>,
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<0 0 0 0 538000000>,
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<0 0 0 0 600000000>;
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clock-cntl-level = "lowsvs", "svs",
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"svs_l1", "nominal", "turbo";
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vmrm-resource-ids = <31 31 31>;
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nrt-device;
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};
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cam_bps: qcom,bps@ac2c000 {
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cell-index = <0>;
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compatible = "qcom,cam-bps", "qcom,cam-bps680";
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reg = <0xac2c000 0xB000>;
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reg-names = "bps_top";
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reg-cam-base = <0x2c000>;
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regulator-names = "bps-vdd";
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bps-vdd-supply = <&cam_cc_bps_gdsc>;
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clock-names =
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"bps_ahb_clk_src",
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"bps_ahb_clk",
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"bps_fast_ahb_clk_src",
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"bps_fast_ahb_clk",
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"bps_clk_src",
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"bps_clk";
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src-clock-name = "bps_clk_src";
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clock-control-debugfs = "true";
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clocks =
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<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
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<&clock_camcc CAM_CC_BPS_AHB_CLK>,
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<&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>,
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<&clock_camcc CAM_CC_BPS_FAST_AHB_CLK>,
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<&clock_camcc CAM_CC_BPS_CLK_SRC>,
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<&clock_camcc CAM_CC_BPS_CLK>;
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clock-rates =
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<80000000 0 100000000 0 200000000 0>,
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<80000000 0 200000000 0 400000000 0>,
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<80000000 0 300000000 0 480000000 0>,
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<80000000 0 400000000 0 600000000 0>,
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<80000000 0 400000000 0 600000000 0>;
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clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
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"turbo";
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nrt-device;
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vmrm-resource-ids = <32 32 32>;
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status = "ok";
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};
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