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38ff34a459008f6e81540ccb2f507bc76bae808b
android_kernel_samsung_sm87…/qcom/kera-qupv3.dtsi
Prasanna S 38ff34a459 ARM: dts: msm: Add QUPv3 and GPI DT nodes on kera 
Add QUPv3(I2C, SPI and UART) and GPI DT nodes on kera.

Change-Id: I3d0db10cd90a59500b29aade5cb9e4017395a1a0
Signed-off-by: Prasanna S <quic_prass@quicinc.com>
2024-11-02 09:10:03 +05:30

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
/* QUPv3 SE Instances
* Qup1 0: SE 0
* Qup1 1: SE 1
* Qup1 2: SE 2
* Qup1 3: SE 3
* Qup1 4: SE 4
* Qup1 5: SE 5
* Qup1 6: SE 6
* Qup1 7: SE 7
* Qup2 0: SE 8
* Qup2 1: SE 9
* Qup2 2: SE 10
* Qup2 3: SE 11
* Qup2 4: SE 12
* Qup2 5: SE 13
* Qup2 6: SE 14
* Qup2 7: SE 15
*/
qup1_gpi_iommu_region: qup1_gpi_iommu_region {
iommu-addresses = <&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xFFE00000>;
};
/* GPI Instance */
gpi_dma1: qcom,gpi-dma@a00000 {
compatible = "qcom,gpi-dma";
reg = <0xa00000 0x60000>;
#dma-cells = <5>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0xb6 0x0>;
qcom,max-num-gpii = <12>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0x1f>;
qcom,ev-factor = <1>;
memory-region = <&qup1_gpi_iommu_region>;
qcom,gpi-ee-offset = <0x10000>;
dma-coherent;
status = "ok";
};
qup1_se_iommu_region: qup1_se_iommu_region {
iommu-addresses = <&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>;
};
/* QUPv3_1 wrapper instance */
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0xac0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0xa3 0x0>;
memory-region = <&qup1_se_iommu_region>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;
ranges;
status = "ok";
qupv3_se0_i2c: i2c@a80000 {
compatible = "qcom,i2c-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
dmas = <&gpi_dma1 0 0 3 64 0>,
<&gpi_dma1 1 0 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se0_spi: spi@a80000 {
compatible = "qcom,spi-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
pinctrl-1 = <&qupv3_se0_spi_sleep>;
dmas = <&gpi_dma1 0 0 1 64 0>,
<&gpi_dma1 1 0 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se1_i2c: i2c@a84000 {
compatible = "qcom,i2c-geni";
reg = <0xa84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
dmas = <&gpi_dma1 0 1 3 64 0>,
<&gpi_dma1 1 1 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se1_spi: spi@a84000 {
compatible = "qcom,spi-geni";
reg = <0xa84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
pinctrl-1 = <&qupv3_se1_spi_sleep>;
dmas = <&gpi_dma1 0 1 1 64 0>,
<&gpi_dma1 1 1 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se2_i2c: i2c@a88000 {
compatible = "qcom,i2c-geni";
reg = <0xa88000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
dmas = <&gpi_dma1 0 2 3 64 0>,
<&gpi_dma1 1 2 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se2_spi: spi@a88000 {
compatible = "qcom,spi-geni";
reg = <0xa88000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
<&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
pinctrl-1 = <&qupv3_se2_spi_sleep>;
dmas = <&gpi_dma1 0 2 1 64 0>,
<&gpi_dma1 1 2 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se3_i2c: i2c@a8c000 {
compatible = "qcom,i2c-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
dmas = <&gpi_dma1 0 3 3 64 0>,
<&gpi_dma1 1 3 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se3_spi: spi@a8c000 {
compatible = "qcom,spi-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>,
<&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>;
pinctrl-1 = <&qupv3_se3_spi_sleep>;
dmas = <&gpi_dma1 0 3 1 64 0>,
<&gpi_dma1 1 3 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se4_i2c: i2c@a90000 {
compatible = "qcom,i2c-geni";
reg = <0xa90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
dmas = <&gpi_dma1 0 4 3 1024 0>,
<&gpi_dma1 1 4 3 1024 0>;
dma-names = "tx", "rx";
qcom,shared;
status = "disabled";
};
/* HS UART Instance */
qupv3_se5_4uart: qcom,qup_uart@a94000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0xa94000 0x4000>;
reg-names = "se_phys";
interrupts-extended = <&intc GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 135 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "active", "sleep", "shutdown";
pinctrl-0 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
pinctrl-1 = <&qupv3_se5_cts>, <&qupv3_se5_rts>,
<&qupv3_se5_tx>, <&qupv3_se5_rx_active>;
pinctrl-2 = <&qupv3_se5_cts>, <&qupv3_se5_rts>,
<&qupv3_se5_tx>, <&qupv3_se5_rx_wake>;
pinctrl-3 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
qcom,wakeup-byte = <0xFD>;
qcom,suspend-ignore-children;
status = "disabled";
};
qupv3_se6_i2c: i2c@a98000 {
compatible = "qcom,i2c-geni";
reg = <0xa98000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
dmas = <&gpi_dma1 0 6 3 64 0>,
<&gpi_dma1 1 6 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se6_spi: spi@a98000 {
compatible = "qcom,spi-geni";
reg = <0xa98000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
pinctrl-1 = <&qupv3_se6_spi_sleep>;
dmas = <&gpi_dma1 0 6 1 64 0>,
<&gpi_dma1 1 6 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se7_i2c: i2c@a9c000 {
compatible = "qcom,i2c-geni";
reg = <0xa9c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>;
pinctrl-1 = <&qupv3_se7_i2c_sleep>;
dmas = <&gpi_dma1 0 7 3 64 0>,
<&gpi_dma1 1 7 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se7_spi: spi@a9c000 {
compatible = "qcom,spi-geni";
reg = <0xa9c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>,
<&qupv3_se7_spi_clk_active>, <&qupv3_se7_spi_cs_active>;
pinctrl-1 = <&qupv3_se7_spi_sleep>;
dmas = <&gpi_dma1 0 7 1 64 0>,
<&gpi_dma1 1 7 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
};
qup2_gpi_iommu_region: qup2_gpi_iommu_region {
iommu-addresses = <&gpi_dma2 0x0 0x100000>, <&gpi_dma2 0x200000 0xFFE00000>;
};
/* GPI Instance */
gpi_dma2: qcom,gpi-dma@800000 {
compatible = "qcom,gpi-dma";
reg = <0x800000 0x60000>;
#dma-cells = <5>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x436 0x0>;
qcom,max-num-gpii = <12>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0x1f>;
qcom,ev-factor = <1>;
memory-region = <&qup2_gpi_iommu_region>;
qcom,gpi-ee-offset = <0x10000>;
dma-coherent;
status = "ok";
};
qup2_se_iommu_region: qup2_se_iommu_region {
iommu-addresses = <&qupv3_2 0x0 0x40000000>, <&qupv3_2 0x50000000 0xb0000000>;
};
/* QUPv3_2 wrapper instance */
qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x8c0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
iommus = <&apps_smmu 0x423 0x0>;
memory-region = <&qup2_se_iommu_region>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;
ranges;
status = "ok";
qupv3_se8_i2c: i2c@880000 {
compatible = "qcom,i2c-geni";
reg = <0x880000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
dmas = <&gpi_dma2 0 0 3 64 0>,
<&gpi_dma2 1 0 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se8_spi: spi@880000 {
compatible = "qcom,spi-geni";
reg = <0x880000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
<&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>;
pinctrl-1 = <&qupv3_se8_spi_sleep>;
dmas = <&gpi_dma2 0 0 1 64 0>,
<&gpi_dma2 1 0 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se9_i2c: i2c@884000 {
compatible = "qcom,i2c-geni";
reg = <0x884000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
dmas = <&gpi_dma2 0 1 3 64 0>,
<&gpi_dma2 1 1 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se9_spi: spi@884000 {
compatible = "qcom,spi-geni";
reg = <0x884000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>,
<&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>;
pinctrl-1 = <&qupv3_se9_spi_sleep>;
dmas = <&gpi_dma2 0 1 1 64 0>,
<&gpi_dma2 1 1 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se10_i2c: i2c@888000 {
compatible = "qcom,i2c-geni";
reg = <0x888000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se10_i2c_sda_active>, <&qupv3_se10_i2c_scl_active>;
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
dmas = <&gpi_dma2 0 2 3 64 0>,
<&gpi_dma2 1 2 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se10_spi: spi@888000 {
compatible = "qcom,spi-geni";
reg = <0x888000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se10_spi_mosi_active>, <&qupv3_se10_spi_miso_active>,
<&qupv3_se10_spi_clk_active>, <&qupv3_se10_spi_cs_active>;
pinctrl-1 = <&qupv3_se10_spi_sleep>;
dmas = <&gpi_dma2 0 2 1 64 0>,
<&gpi_dma2 1 2 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se11_i2c: i2c@88c000 {
compatible = "qcom,i2c-geni";
reg = <0x88c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se11_i2c_sda_active>, <&qupv3_se11_i2c_scl_active>;
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
dmas = <&gpi_dma2 0 3 3 64 0>,
<&gpi_dma2 1 3 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se11_spi: spi@88c000 {
compatible = "qcom,spi-geni";
reg = <0x88c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se11_spi_mosi_active>, <&qupv3_se11_spi_miso_active>,
<&qupv3_se11_spi_clk_active>, <&qupv3_se11_spi_cs_active>;
pinctrl-1 = <&qupv3_se11_spi_sleep>;
dmas = <&gpi_dma2 0 3 1 64 0>,
<&gpi_dma2 1 3 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se12_i2c: i2c@890000 {
compatible = "qcom,i2c-geni";
reg = <0x890000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se12_i2c_sda_active>, <&qupv3_se12_i2c_scl_active>;
pinctrl-1 = <&qupv3_se12_i2c_sleep>;
dmas = <&gpi_dma2 0 4 3 64 0>,
<&gpi_dma2 1 4 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se12_spi: spi@890000 {
compatible = "qcom,spi-geni";
reg = <0x890000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se12_spi_mosi_active>, <&qupv3_se12_spi_miso_active>,
<&qupv3_se12_spi_clk_active>, <&qupv3_se12_spi_cs_active>;
pinctrl-1 = <&qupv3_se12_spi_sleep>;
dmas = <&gpi_dma2 0 4 1 64 0>,
<&gpi_dma2 1 4 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
/* Debug UART Instance */
qupv3_se13_2uart: qcom,qup_uart@894000 {
compatible = "qcom,geni-debug-uart";
reg = <0x894000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_2uart_tx_active>, <&qupv3_se13_2uart_rx_active>;
pinctrl-1 = <&qupv3_se13_2uart_sleep>;
status = "disabled";
};
qupv3_se14_i2c: i2c@898000 {
compatible = "qcom,i2c-geni";
reg = <0x898000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se14_i2c_sda_active>, <&qupv3_se14_i2c_scl_active>;
pinctrl-1 = <&qupv3_se14_i2c_sleep>;
dmas = <&gpi_dma2 0 6 3 64 0>,
<&gpi_dma2 1 6 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se14_spi: spi@898000 {
compatible = "qcom,spi-geni";
reg = <0x898000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se14_spi_mosi_active>, <&qupv3_se14_spi_miso_active>,
<&qupv3_se14_spi_clk_active>, <&qupv3_se14_spi_cs_active>;
pinctrl-1 = <&qupv3_se14_spi_sleep>;
dmas = <&gpi_dma2 0 6 1 64 0>,
<&gpi_dma2 1 6 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se15_i2c: i2c@89c000 {
compatible = "qcom,i2c-geni";
reg = <0x89c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>;
pinctrl-1 = <&qupv3_se15_i2c_sleep>;
dmas = <&gpi_dma2 0 7 3 64 0>,
<&gpi_dma2 1 7 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se15_spi: spi@89c000 {
compatible = "qcom,spi-geni";
reg = <0x89c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>,
<&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>;
pinctrl-1 = <&qupv3_se15_spi_sleep>;
dmas = <&gpi_dma2 0 7 1 64 0>,
<&gpi_dma2 1 7 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
};
};
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