38ff34a459
Add QUPv3(I2C, SPI and UART) and GPI DT nodes on kera. Change-Id: I3d0db10cd90a59500b29aade5cb9e4017395a1a0 Signed-off-by: Prasanna S <quic_prass@quicinc.com>
1653 lines
27 KiB
Plaintext
1653 lines
27 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&tlmm {
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qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
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qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active {
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mux {
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pins = "gpio28";
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function = "qup1_se0_l0";
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};
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config {
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pins = "gpio28";
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drive-strength = <2>;
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bias-pull-up;
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qcom,i2c_pull;
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};
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};
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qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active {
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mux {
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pins = "gpio29";
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function = "qup1_se0_l1";
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};
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config {
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pins = "gpio29";
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drive-strength = <2>;
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bias-pull-up;
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qcom,i2c_pull;
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};
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};
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qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
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mux {
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pins = "gpio28", "gpio29";
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function = "gpio";
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};
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config {
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pins = "gpio28", "gpio29";
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drive-strength = <2>;
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};
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};
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};
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qupv3_se0_spi_pins: qupv3_se0_spi_pins {
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qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active {
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mux {
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pins = "gpio28";
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function = "qup1_se0_l0";
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};
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config {
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pins = "gpio28";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active {
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mux {
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pins = "gpio29";
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function = "qup1_se0_l1";
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};
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config {
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pins = "gpio29";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active {
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mux {
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pins = "gpio30";
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function = "qup1_se0_l2";
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};
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config {
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pins = "gpio30";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active {
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mux {
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pins = "gpio31";
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function = "qup1_se0_l3";
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};
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config {
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pins = "gpio31";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
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mux {
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pins = "gpio28", "gpio29",
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"gpio30", "gpio31";
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function = "gpio";
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};
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config {
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pins = "gpio28", "gpio29",
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"gpio30", "gpio31";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
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qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active {
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mux {
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pins = "gpio32";
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function = "qup1_se1_l0";
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};
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config {
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pins = "gpio32";
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drive-strength = <2>;
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bias-pull-up;
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qcom,i2c_pull;
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};
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};
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qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active {
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mux {
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pins = "gpio33";
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function = "qup1_se1_l1";
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};
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config {
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pins = "gpio33";
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drive-strength = <2>;
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bias-pull-up;
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qcom,i2c_pull;
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};
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};
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qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
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mux {
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pins = "gpio32", "gpio33";
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function = "gpio";
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};
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config {
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pins = "gpio32", "gpio33";
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drive-strength = <2>;
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};
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};
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};
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qupv3_se1_spi_pins: qupv3_se1_spi_pins {
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qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active {
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mux {
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pins = "gpio32";
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function = "qup1_se1_l0";
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};
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config {
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pins = "gpio32";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active {
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mux {
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pins = "gpio33";
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function = "qup1_se1_l1";
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};
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config {
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pins = "gpio33";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active {
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mux {
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pins = "gpio34";
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function = "qup1_se1_l2";
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};
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config {
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pins = "gpio34";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active {
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mux {
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pins = "gpio35";
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function = "qup1_se1_l3";
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};
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config {
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pins = "gpio35";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
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mux {
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pins = "gpio32", "gpio33",
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"gpio34", "gpio35";
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function = "gpio";
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};
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config {
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pins = "gpio32", "gpio33",
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"gpio34", "gpio35";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
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qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active {
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mux {
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pins = "gpio52";
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function = "qup1_se2_l0";
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};
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config {
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pins = "gpio52";
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drive-strength = <2>;
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bias-pull-up;
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qcom,i2c_pull;
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};
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};
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qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active {
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mux {
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pins = "gpio53";
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function = "qup1_se2_l1";
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};
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config {
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pins = "gpio53";
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drive-strength = <2>;
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bias-pull-up;
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qcom,i2c_pull;
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};
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};
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qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
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mux {
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pins = "gpio52", "gpio53";
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function = "gpio";
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};
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config {
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pins = "gpio52", "gpio53";
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drive-strength = <2>;
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};
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};
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};
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qupv3_se2_spi_pins: qupv3_se2_spi_pins {
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qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active {
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mux {
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pins = "gpio52";
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function = "qup1_se2_l0";
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};
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config {
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pins = "gpio52";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active {
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mux {
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pins = "gpio53";
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function = "qup1_se2_l1";
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};
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config {
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pins = "gpio53";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active {
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mux {
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pins = "gpio54";
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function = "qup1_se2_l2_mira";
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};
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config {
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pins = "gpio54";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active {
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mux {
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pins = "gpio55";
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function = "qup1_se2_l3_mira";
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};
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config {
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pins = "gpio55";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
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mux {
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pins = "gpio52", "gpio53",
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"gpio54", "gpio55";
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function = "gpio";
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};
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config {
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pins = "gpio52", "gpio53",
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"gpio54", "gpio55";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
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qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active {
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mux {
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pins = "gpio44";
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function = "qup1_se3_l0";
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};
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config {
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pins = "gpio44";
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drive-strength = <2>;
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bias-pull-up;
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qcom,i2c_pull;
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};
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};
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qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active {
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mux {
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pins = "gpio45";
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function = "qup1_se3_l1";
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};
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config {
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pins = "gpio45";
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drive-strength = <2>;
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bias-pull-up;
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qcom,i2c_pull;
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};
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};
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qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
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mux {
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pins = "gpio44", "gpio45";
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function = "gpio";
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};
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config {
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pins = "gpio44", "gpio45";
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drive-strength = <2>;
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};
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};
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};
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qupv3_se3_spi_pins: qupv3_se3_spi_pins {
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qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active {
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mux {
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pins = "gpio44";
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function = "qup1_se3_l0";
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};
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config {
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pins = "gpio44";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active {
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mux {
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pins = "gpio45";
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function = "qup1_se3_l1";
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};
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config {
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pins = "gpio45";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active {
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mux {
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pins = "gpio46";
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function = "qup1_se3_l2";
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};
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config {
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pins = "gpio46";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active {
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mux {
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pins = "gpio47";
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function = "qup1_se3_l3";
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};
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config {
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pins = "gpio47";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
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mux {
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pins = "gpio44", "gpio45",
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"gpio46", "gpio47";
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function = "gpio";
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};
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config {
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pins = "gpio44", "gpio45",
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"gpio46", "gpio47";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
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qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active {
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mux {
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pins = "gpio36";
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function = "qup1_se4_l0";
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};
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config {
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pins = "gpio36";
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drive-strength = <2>;
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bias-pull-up;
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qcom,i2c_pull;
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};
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};
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qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active {
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mux {
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pins = "gpio37";
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function = "qup1_se4_l1";
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};
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config {
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pins = "gpio37";
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drive-strength = <2>;
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bias-pull-up;
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qcom,i2c_pull;
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};
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};
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qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
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mux {
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pins = "gpio36", "gpio37";
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function = "gpio";
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};
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config {
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pins = "gpio36", "gpio37";
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drive-strength = <2>;
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};
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};
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};
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qupv3_se5_4uart_pins: qupv3_se5_4uart_pins {
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qupv3_se5_default_cts: qupv3_se5_default_cts {
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mux {
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pins = "gpio132";
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function = "gpio";
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};
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config {
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pins = "gpio132";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se5_default_rts: qupv3_se5_default_rts {
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mux {
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pins = "gpio133";
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function = "gpio";
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};
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config {
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pins = "gpio133";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se5_default_tx: qupv3_se5_default_tx {
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mux {
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pins = "gpio134";
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function = "gpio";
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};
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config {
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pins = "gpio134";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se5_default_rx: qupv3_se5_default_rx {
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mux {
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pins = "gpio135";
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function = "gpio";
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};
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config {
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pins = "gpio135";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se5_cts: qupv3_se5_cts {
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mux {
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pins = "gpio132";
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function = "qup1_se5_l0";
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};
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config {
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pins = "gpio132";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se5_rts: qupv3_se5_rts {
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mux {
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pins = "gpio133";
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function = "qup1_se5_l1";
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};
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config {
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pins = "gpio133";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se5_tx: qupv3_se5_tx {
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mux {
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pins = "gpio134";
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function = "qup1_se5_l2";
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};
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config {
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pins = "gpio134";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se5_rx_active: qupv3_se5_rx_active {
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mux {
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pins = "gpio135";
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function = "qup1_se5_l3";
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};
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config {
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pins = "gpio135";
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drive-strength = <2>;
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bias-disable;
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};
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};
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/* RX to be in gpio mode for sleep config */
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qupv3_se5_rx_wake: qupv3_se5_rx_wake {
|
|
mux {
|
|
pins = "gpio135";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio135";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
|
|
qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio40";
|
|
function = "qup1_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio54";
|
|
function = "qup1_se6_l1_mirb";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio54";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
|
|
mux {
|
|
pins = "gpio40", "gpio54";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40", "gpio54";
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_pins: qupv3_se6_spi_pins {
|
|
qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active {
|
|
mux {
|
|
pins = "gpio40";
|
|
function = "qup1_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio54";
|
|
function = "qup1_se6_l1_mirb";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio54";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active {
|
|
mux {
|
|
pins = "gpio42";
|
|
function = "qup1_se6_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active {
|
|
mux {
|
|
pins = "gpio55";
|
|
function = "qup1_se6_l3_mirb";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio55";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
|
|
mux {
|
|
pins = "gpio40", "gpio54",
|
|
"gpio42", "gpio55";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40", "gpio54",
|
|
"gpio42", "gpio55";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
|
|
qupv3_se7_i2c_sda_active: qupv3_se7_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio81";
|
|
function = "qup1_se7_l0_mira";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio81";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_i2c_scl_active: qupv3_se7_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio80";
|
|
function = "qup1_se7_l1_mira";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio80";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
|
|
mux {
|
|
pins = "gpio81", "gpio80";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio81", "gpio80";
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_pins: qupv3_se7_spi_pins {
|
|
qupv3_se7_spi_miso_active: qupv3_se7_spi_miso_active {
|
|
mux {
|
|
pins = "gpio81";
|
|
function = "qup1_se7_l0_mira";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio81";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_mosi_active: qupv3_se7_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio80";
|
|
function = "qup1_se7_l1_mira";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio80";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_clk_active: qupv3_se7_spi_clk_active {
|
|
mux {
|
|
pins = "gpio114";
|
|
function = "qup1_se7_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio114";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_cs_active: qupv3_se7_spi_cs_active {
|
|
mux {
|
|
pins = "gpio78";
|
|
function = "qup1_se7_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio78";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
|
|
mux {
|
|
pins = "gpio81", "gpio80",
|
|
"gpio114", "gpio78";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio81", "gpio80",
|
|
"gpio114", "gpio78";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
|
|
qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio0";
|
|
function = "qup2_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio1";
|
|
function = "qup2_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio1";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
|
|
mux {
|
|
pins = "gpio0", "gpio1";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0", "gpio1";
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_pins: qupv3_se8_spi_pins {
|
|
qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active {
|
|
mux {
|
|
pins = "gpio0";
|
|
function = "qup2_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio1";
|
|
function = "qup2_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio1";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active {
|
|
mux {
|
|
pins = "gpio2";
|
|
function = "qup2_se0_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio2";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active {
|
|
mux {
|
|
pins = "gpio3";
|
|
function = "qup2_se0_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio3";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
|
|
mux {
|
|
pins = "gpio0", "gpio1",
|
|
"gpio2", "gpio3";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0", "gpio1",
|
|
"gpio2", "gpio3";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
|
|
qupv3_se9_i2c_sda_active: qupv3_se9_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio4";
|
|
function = "qup2_se1_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i2c_scl_active: qupv3_se9_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio5";
|
|
function = "qup2_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio5";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
|
|
mux {
|
|
pins = "gpio4", "gpio5";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4", "gpio5";
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_pins: qupv3_se9_spi_pins {
|
|
qupv3_se9_spi_miso_active: qupv3_se9_spi_miso_active {
|
|
mux {
|
|
pins = "gpio4";
|
|
function = "qup2_se1_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_mosi_active: qupv3_se9_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio5";
|
|
function = "qup2_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio5";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_clk_active: qupv3_se9_spi_clk_active {
|
|
mux {
|
|
pins = "gpio6";
|
|
function = "qup2_se1_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_cs_active: qupv3_se9_spi_cs_active {
|
|
mux {
|
|
pins = "gpio7";
|
|
function = "qup2_se1_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio7";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
|
|
mux {
|
|
pins = "gpio4", "gpio5",
|
|
"gpio6", "gpio7";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4", "gpio5",
|
|
"gpio6", "gpio7";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
|
|
qupv3_se10_i2c_sda_active: qupv3_se10_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "qup2_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i2c_scl_active: qupv3_se10_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "qup2_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
|
|
mux {
|
|
pins = "gpio8", "gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8", "gpio9";
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_pins: qupv3_se10_spi_pins {
|
|
qupv3_se10_spi_miso_active: qupv3_se10_spi_miso_active {
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "qup2_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_mosi_active: qupv3_se10_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "qup2_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_clk_active: qupv3_se10_spi_clk_active {
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "qup2_se2_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_cs_active: qupv3_se10_spi_cs_active {
|
|
mux {
|
|
pins = "gpio11";
|
|
function = "qup2_se2_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio11";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
|
|
mux {
|
|
pins = "gpio8", "gpio9",
|
|
"gpio10", "gpio11";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8", "gpio9",
|
|
"gpio10", "gpio11";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
|
|
qupv3_se11_i2c_sda_active: qupv3_se11_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio79";
|
|
function = "qup2_se3_l0_mira";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio79";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_scl_active: qupv3_se11_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio97";
|
|
function = "qup2_se3_l1_mira";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio97";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
|
|
mux {
|
|
pins = "gpio79", "gpio97";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio79", "gpio97";
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_pins: qupv3_se11_spi_pins {
|
|
qupv3_se11_spi_miso_active: qupv3_se11_spi_miso_active {
|
|
mux {
|
|
pins = "gpio79";
|
|
function = "qup2_se3_l0_mira";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio79";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_mosi_active: qupv3_se11_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio97";
|
|
function = "qup2_se3_l1_mira";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio97";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_clk_active: qupv3_se11_spi_clk_active {
|
|
mux {
|
|
pins = "gpio100";
|
|
function = "qup2_se3_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio100";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_cs_active: qupv3_se11_spi_cs_active {
|
|
mux {
|
|
pins = "gpio116";
|
|
function = "qup2_se3_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio116";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
|
|
mux {
|
|
pins = "gpio79", "gpio97",
|
|
"gpio100", "gpio116";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio79", "gpio97",
|
|
"gpio100", "gpio116";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
|
|
qupv3_se12_i2c_sda_active: qupv3_se12_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio12";
|
|
function = "qup2_se4_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_i2c_scl_active: qupv3_se12_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "qup2_se4_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
|
|
mux {
|
|
pins = "gpio12", "gpio13";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12", "gpio13";
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_pins: qupv3_se12_spi_pins {
|
|
qupv3_se12_spi_miso_active: qupv3_se12_spi_miso_active {
|
|
mux {
|
|
pins = "gpio12";
|
|
function = "qup2_se4_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_mosi_active: qupv3_se12_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "qup2_se4_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_clk_active: qupv3_se12_spi_clk_active {
|
|
mux {
|
|
pins = "gpio26";
|
|
function = "qup2_se4_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio26";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_cs_active: qupv3_se12_spi_cs_active {
|
|
mux {
|
|
pins = "gpio27";
|
|
function = "qup2_se4_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
|
|
mux {
|
|
pins = "gpio12", "gpio13",
|
|
"gpio26", "gpio27";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12", "gpio13",
|
|
"gpio26", "gpio27";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se13_2uart_pins: qupv3_se13_2uart_pins {
|
|
qupv3_se13_2uart_tx_active: qupv3_se13_2uart_tx_active {
|
|
mux {
|
|
pins = "gpio18";
|
|
function = "qup2_se5_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio18";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_2uart_rx_active: qupv3_se13_2uart_rx_active {
|
|
mux {
|
|
pins = "gpio19";
|
|
function = "qup2_se5_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio19";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_2uart_sleep: qupv3_se13_2uart_sleep {
|
|
mux {
|
|
pins = "gpio18", "gpio19";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio18", "gpio19";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
|
|
qupv3_se14_i2c_sda_active: qupv3_se14_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "qup2_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_i2c_scl_active: qupv3_se14_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio21";
|
|
function = "qup2_se6_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
|
|
mux {
|
|
pins = "gpio20", "gpio21";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20", "gpio21";
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se14_spi_pins: qupv3_se14_spi_pins {
|
|
qupv3_se14_spi_miso_active: qupv3_se14_spi_miso_active {
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "qup2_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_spi_mosi_active: qupv3_se14_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio21";
|
|
function = "qup2_se6_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_spi_clk_active: qupv3_se14_spi_clk_active {
|
|
mux {
|
|
pins = "gpio22";
|
|
function = "qup2_se6_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio22";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_spi_cs_active: qupv3_se14_spi_cs_active {
|
|
mux {
|
|
pins = "gpio23";
|
|
function = "qup2_se6_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
|
|
mux {
|
|
pins = "gpio20", "gpio21",
|
|
"gpio22", "gpio23";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20", "gpio21",
|
|
"gpio22", "gpio23";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
|
|
qupv3_se15_i2c_sda_active: qupv3_se15_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio27";
|
|
function = "qup2_se7_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_i2c_scl_active: qupv3_se15_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio26";
|
|
function = "qup2_se7_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio26";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
|
|
mux {
|
|
pins = "gpio27", "gpio26";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27", "gpio26";
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se15_spi_pins: qupv3_se15_spi_pins {
|
|
qupv3_se15_spi_miso_active: qupv3_se15_spi_miso_active {
|
|
mux {
|
|
pins = "gpio27";
|
|
function = "qup2_se7_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_spi_mosi_active: qupv3_se15_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio26";
|
|
function = "qup2_se7_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio26";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_spi_clk_active: qupv3_se15_spi_clk_active {
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "qup2_se7_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_spi_cs_active: qupv3_se15_spi_cs_active {
|
|
mux {
|
|
pins = "gpio12";
|
|
function = "qup2_se7_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
|
|
mux {
|
|
pins = "gpio27", "gpio26",
|
|
"gpio13", "gpio12";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27", "gpio26",
|
|
"gpio13", "gpio12";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
};
|