396a58be1e
Added secure indicator UID in dts to provide access. Signed-off-by: Shivangi Kesharwani <quic_skesharw@quicinc.com>
407 lines
9.4 KiB
Plaintext
407 lines
9.4 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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qcom,msm-id = <457 0x10000>, <482 0x10000>;
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interrupt-parent = <&vgic>;
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qcom,mem-buf {
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compatible = "qcom,mem-buf";
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qcom,mem-buf-capabilities = "consumer";
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qcom,vmid = <45>;
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};
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qcom,mem-buf-msgq {
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compatible = "qcom,mem-buf-msgq";
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qcom,msgq-names = "trusted_vm";
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};
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chosen {
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bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable root=/dev/vda init=/sbin/init";
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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CPU0: cpu@0 {
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN
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&CLUSTER_PWR_DWN>;
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};
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CPU1: cpu@100 {
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN
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&CLUSTER_PWR_DWN>;
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};
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};
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idle-states {
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CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <600>;
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exit-latency-us = <1550>;
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min-residency-us = <4791>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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CLUSTER_PWR_DWN: d4 { /* C4+D4 */
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compatible = "arm,idle-state";
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idle-state-name = "l3-pc";
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entry-latency-us = <1050>;
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exit-latency-us = <2500>;
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min-residency-us = <5309>;
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arm,psci-suspend-param = <0x40000044>;
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local-timer-stop;
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};
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};
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qrtr-gunyah {
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compatible = "qcom,qrtr-gunyah";
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gunyah-label = <3>;
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};
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qcom,vm-config {
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compatible = "qcom,vm-1.0";
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vm-type = "aarch64-guest";
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boot-config = "fdt,unified";
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os-type = "linux";
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kernel-entry-segment = "kernel";
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kernel-entry-offset = <0x0 0x0>;
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vendor = "QTI";
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image-name = "qcom,trustedvm";
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qcom,pasid = <0x0 0x1c>;
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qcom,qtee-config-info = "p=7C,8F,97,C8,159,199,7F1;";
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qcom,secdomain-ids = <45>;
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qcom,primary-vm-index = <0>;
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vm-uri = "vmuid/trusted-ui";
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vm-guid = "3f4d154a-92d3-54d0-9241-08e34c8bc670";
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qcom,sensitive;
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iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0
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0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
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0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
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0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1
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0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1
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0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;
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gic-irq-ranges = <283 283>; /* PVM->SVM IRQ transfer */
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memory {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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base-address = <0x0 0xe0c00000>;
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size-min = <0x0 0x7a00000>; /* 122 MB */
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};
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segments {
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ramdisk = <2>; /* 8MB */
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};
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vcpus {
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config = "/cpus";
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affinity = "static";
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affinity-map = <0x5 0x6>;
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sched-priority = <0>; /* relative to PVM */
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sched-timeslice = <2000>; /* in ms */
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};
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interrupts {
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config = &vgic;
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};
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vdevices {
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generate = "/hypervisor";
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rm-rpc {
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vdevice-type = "rm-rpc";
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generate = "/hypervisor/qcom,resource-mgr";
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console-dev;
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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qcom,label = <0x1>;
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};
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virtio-mmio@0 {
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vdevice-type = "virtio-mmio";
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generate = "/virtio-mmio";
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peer-default;
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vqs-num = <0x1>;
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push-compatible = "virtio,mmio";
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dma-coherent;
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dma_base = <0x0 0x0>;
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memory {
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qcom,label = <0x11>;
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#address-cells = <0x2>;
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base = <0x0 0xFFEFC000>;
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};
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};
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swiotlb-shm {
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vdevice-type = "shm";
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generate = "/swiotlb";
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push-compatible = "swiotlb";
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peer-default;
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dma_base = <0x0 0x4000>;
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memory {
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qcom,label = <0x12>;
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#address-cells = <0x2>;
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base = <0x0 0xFFF00000>;
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};
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};
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mem-buf-message-queue-pair {
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vdevice-type = "message-queue-pair";
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generate = "/hypervisor/membuf-msgq-pair";
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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peer-default;
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qcom,label = <0x0000001>;
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};
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display-message-queue-pair {
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vdevice-type = "message-queue-pair";
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generate = "/hypervisor/display-msgq-pair";
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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peer-default;
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qcom,label = <0x0000002>;
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};
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gvsock-message-queue-pair {
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vdevice-type = "message-queue-pair";
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generate = "/hypervisor/gvsock-msgq-pair";
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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peer = "vm-name:qcom,oemvm";
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qcom,label = <0x0000003>;
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};
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qrtr-shm {
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vdevice-type = "shm-doorbell";
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generate = "/hypervisor/qrtr-shm";
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push-compatible = "qcom,qrtr-gunyah-gen";
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peer-default;
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memory {
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qcom,label = <0x3>;
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allocate-base;
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};
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};
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gpiomem0 {
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vdevice-type = "iomem";
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patch = "/soc/tlmm-vm-mem-access";
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push-compatible = "qcom,tlmm-vm-mem-access";
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peer-default;
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memory {
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qcom,label = <0x8>;
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qcom,mem-info-tag = <0x3>;
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allocate-base;
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};
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};
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test-dbl {
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vdevice-type = "doorbell";
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generate = "/hypervisor/test-dbl";
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qcom,label = <0x4>;
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peer-default;
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};
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test-dbl-source {
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vdevice-type = "doorbell-source";
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generate = "/hypervisor/test-dbl-source";
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qcom,label = <0x4>;
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peer-default;
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};
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};
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};
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firmware: firmware {
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scm {
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compatible = "qcom,scm";
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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spmi_bus: qcom,spmi@c42d000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0xc42d000 0x4000>,
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<0xc400000 0x3000>,
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<0xc500000 0x400000>,
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<0xc440000 0x80000>,
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<0xc4c0000 0x10000>;
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reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
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#address-cells = <2>;
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#size-cells = <0>;
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cell-index = <0>;
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qcom,channel = <0>;
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qcom,ee = <0>;
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qcom,bus-id = <0>;
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};
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vm_tlmm_irq: vm-tlmm-irq@0 {
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compatible = "qcom,tlmm-vm-irq";
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reg = <0x0 0x0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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tlmm: pinctrl@f000000 {
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reg = <0x0F000000 0x1000000>;
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interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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/* Valid pins */
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gpios = /bits/ 16 <64 65 66 67 0 4 86 87 16 17 18 19 20 21>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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tlmm-vm-mem-access {
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compatible = "qcom,tlmm-vm-mem-access";
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tlmm-vm-gpio-list = <&tlmm 64 0 &tlmm 65 0 &tlmm 66 0 &tlmm 67 0 &tlmm 0 0
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&tlmm 4 0 &tlmm 86 0 &tlmm 87 0 &tlmm 16 0 &tlmm 17 0
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&tlmm 18 0 &tlmm 19 0 &tlmm 20 0 &tlmm 21 0>;
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};
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vgic: interrupt-controller@17100000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x17100000 0x10000>, /* GICD */
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<0x17180000 0x100000>; /* GICR * 8 */
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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always-on;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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/*
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* QUPv3 Instances
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* North 4 : SE 4
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*/
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qup_iommu_group: qup_common_iommu_group {
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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};
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/* GPI */
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gpi_dma0: qcom,gpi-dma@900000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x900000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0x5b8 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <12>;
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qcom,gpii-mask = <0x80>;
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qcom,ev-factor = <2>;
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qcom,gpi-ee-offset = <0x10000>;
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qcom,le-vm;
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status = "ok";
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};
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/* QUPv3_0 wrapper instance: North QUP */
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qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x9c0000 0x2000>;
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iommus = <&apps_smmu 0x5b8 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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status = "ok";
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/* I2C SE */
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qupv3_se4_i2c: i2c@990000 {
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compatible = "qcom,i2c-geni";
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reg = <0x990000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&gpi_dma0 0 4 3 64 0>,
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<&gpi_dma0 1 4 3 64 0>;
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dma-names = "tx", "rx";
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qcom,le-vm;
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status = "disabled";
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};
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qupv3_se4_spi: spi@990000 {
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compatible = "qcom,spi-geni";
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reg = <0x990000 0x4000>;
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reg-names = "se_phys";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&gpi_dma0 0 4 1 64 0>,
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<&gpi_dma0 1 4 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,le-vm;
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status = "disabled";
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};
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};
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qcom_smcinvoke {
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compatible = "qcom,smcinvoke";
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};
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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qcom,custom-bridge-size = <512>;
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qcom,support-hypervisor;
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};
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qcom,test-dbl {
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compatible = "qcom,gh-dbl";
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qcom,label = <0x4>;
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};
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};
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#include "waipio-vm-dma-heaps.dtsi"
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#include "msm-arm-smmu-waipio-vm.dtsi"
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