6317952c04
Set RX settings mode to zero for Ultrashort channel settings for TUNA PCIe controller. Change-Id: Iff8a09f2ae474e8b8bec35a4dbbdc3df6fb40147 Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
303 lines
7.9 KiB
Plaintext
303 lines
7.9 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,gcc-tuna.h>
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#include <dt-bindings/gpio/gpio.h>
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&soc {
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pcie0: pcie@1c00000 {
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compatible = "qcom,pci-msm";
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device_type = "pci";
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reg = <0x1c00000 0x3000>,
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<0x1c06000 0x2000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>,
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<0x1c03000 0x1000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3d00000>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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msi-map = <0x0 &gic_its 0x1400 0x1>,
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<0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */
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perst-gpio = <&tlmm 33 GPIO_ACTIVE_HIGH>;
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wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_perst_default
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&pcie0_clkreq_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_perst_default
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&pcie0_clkreq_sleep
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&pcie0_wake_default>;
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gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
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gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
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vreg-1p2-supply = <&L4B>;
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vreg-0p9-supply = <&L2B>;
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vreg-qref-supply = <&L2B>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-mx-supply = <&VDD_MXA_LEVEL>;
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qcom,vreg-1p2-voltage-level = <1200000 1200000 15010>;
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qcom,vreg-0p9-voltage-level = <912000 880000 92070>;
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qcom,vreg-qref-voltage-level = <880000 880000 46800>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000>;
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interconnect-names = "icc_path";
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interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
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<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
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<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
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<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
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<&gcc GCC_PCIE_0_PIPE_DIV2_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
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<&pcie_0_pipe_clk>;
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clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
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"pcie_aux_clk", "pcie_cfg_ahb_clk",
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"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
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"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
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"pcie_rate_change_clk",
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"gcc_ddrss_pcie_sf_qtb_clk",
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"pcie_aggre_noc_axi_clk",
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"gcc_cnoc_pcie_sf_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk",
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"pcie_0_pipe_div2_clk", "pcie_pipe_clk_mux",
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"pcie_pipe_clk_ext_src";
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qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
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<100000000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
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clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
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<0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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dma-coherent;
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qcom,smmu-sid-base = <0x1400>;
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iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
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<0x100 &apps_smmu 0x1401 0x1>;
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qcom,boot-option = <0x1>;
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qcom,aux-clk-freq = <20>; /* 19.2 MHz */
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qcom,l1-2-th-scale = <2>;
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qcom,l1-2-th-value = <150>;
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qcom,ep-latency = <10>;
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qcom,num-parf-testbus-sel = <0xb9>;
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qcom,drv-name = "lpass";
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qcom,drv-l1ss-timeout-us = <5000>;
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qcom,pcie-phy-ver = <112>;
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qcom,phy-status-offset = <0x214>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x240>;
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qcom,phy-sequence = <0x0240 0x03 0x0
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0x00c0 0x01 0x0
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0x00cc 0x62 0x0
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0x00d0 0x02 0x0
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0x0060 0xf8 0x0
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0x0064 0x01 0x0
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0x0000 0x93 0x0
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0x0004 0x01 0x0
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0x00e0 0x90 0x0
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0x00e4 0x82 0x0
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0x00f4 0x07 0x0
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0x0070 0x02 0x0
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0x0010 0x02 0x0
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0x0074 0x16 0x0
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0x0014 0x16 0x0
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0x0078 0x36 0x0
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0x0018 0x36 0x0
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0x0110 0x08 0x0
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0x00bc 0x0a 0x0
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0x0120 0x42 0x0
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0x0080 0x04 0x0
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0x0084 0x0d 0x0
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0x0020 0x0a 0x0
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0x0024 0x1a 0x0
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0x0088 0x41 0x0
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0x0028 0x34 0x0
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0x0090 0xab 0x0
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0x0094 0xaa 0x0
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0x0098 0x01 0x0
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0x0030 0x55 0x0
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0x0034 0x55 0x0
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0x0038 0x01 0x0
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0x0140 0x14 0x0
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0x0164 0x34 0x0
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0x003c 0x01 0x0
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0x001c 0x04 0x0
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0x0174 0x16 0x0
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0x01bc 0x0f 0x0
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0x0170 0xa0 0x0
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0x11a4 0x38 0x0
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0x10dc 0x11 0x0
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0x1160 0xbf 0x0
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0x1164 0xbf 0x0
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0x1168 0xb7 0x0
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0x116c 0xea 0x0
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0x115c 0x3f 0x0
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0x1174 0x5c 0x0
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0x1178 0x9c 0x0
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0x117c 0x1a 0x0
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0x1180 0x8f 0x0
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0x1170 0xdc 0x0
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0x1188 0x94 0x0
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0x118c 0x5b 0x0
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0x1190 0x1a 0x0
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0x1194 0x8f 0x0
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0x10cc 0x00 0x0
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0x1008 0x09 0x0
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0x1014 0x05 0x0
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0x104c 0x08 0x0
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0x1050 0x08 0x0
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0x10d8 0x0f 0x0
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0x1118 0x1c 0x0
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0x10f8 0x07 0x0
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0x11f8 0x08 0x0
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0x1600 0x00 0x0
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0x0e84 0x15 0x0
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0x0e90 0x3f 0x0
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0x0ee4 0x02 0x0
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0x0e40 0x06 0x0
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0x0e3c 0x18 0x0
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0x19a4 0x38 0x0
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0x18dc 0x11 0x0
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0x1960 0xbf 0x0
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0x1964 0xbf 0x0
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0x1968 0xb7 0x0
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0x196c 0xea 0x0
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0x195c 0x3f 0x0
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0x1974 0x5c 0x0
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0x1978 0x9c 0x0
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0x197c 0x1a 0x0
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0x1980 0x8f 0x0
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0x1970 0xdc 0x0
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0x1988 0x94 0x0
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0x198c 0x5b 0x0
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0x1990 0x1a 0x0
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0x1994 0x8f 0x0
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0x18cc 0x00 0x0
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0x1808 0x09 0x0
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0x1814 0x05 0x0
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0x184c 0x08 0x0
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0x1850 0x08 0x0
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0x18d8 0x0f 0x0
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0x1918 0x1c 0x0
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0x18f8 0x07 0x0
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0x19f8 0x08 0x0
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0x1684 0x15 0x0
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0x1690 0x3f 0x0
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0x16e4 0x02 0x0
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0x1640 0x06 0x0
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0x163c 0x18 0x0
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0x02dc 0x05 0x0
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0x0388 0x77 0x0
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0x0398 0x0b 0x0
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0x06a4 0x1e 0x0
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0x06f4 0x27 0x0
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0x03e0 0x0f 0x0
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0x060c 0x1d 0x0
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0x0614 0x07 0x0
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0x0620 0xc1 0x0
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0x0694 0x00 0x0
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0x03d0 0x8c 0x0
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0x0368 0x17 0x0
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0x0370 0x2e 0x0
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0x0200 0x00 0x0
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0x0244 0x03 0x0>;
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status = "disabled";
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@17110040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17110040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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};
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