android_kernel_samsung_sm8750-devicetrees/qcom/parrot-vm.dtsi

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include "waipio-vm.dtsi"
#include <dt-bindings/clock/qcom,gcc-parrot.h>

/ {
	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
			<633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>;
	interrupt-parent = <&vgic>;

	qcom,vm-config {
		iomemory-ranges = <0x0 0x0a28000 0x0 0x0a28000 0x0 0x4000 0x0
				0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
				0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
				0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1
				0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1
				0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;

		gic-irq-ranges = <325 325>; /* PVM->SVM IRQ transfer */
		vdevices {
			gvsock-message-queue-pair {
				status = "disabled";
			};
		};
	};
};

&soc {

	/delete-node/ interrupt-controller@17100000;

	qcom,spmi@c42d000 {
		status = "disabled";
	};

	gcc: clock-controller@100000 {
		compatible = "qcom,dummycc";
		clock-output-names = "gcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	vgic: interrupt-controller@17200000 {
		compatible = "arm,gic-v3";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17200000 0x10000>,     /* GICD */
		<0x17260000 0x100000>;    /* GICR * 8 */
	};

	tlmm: pinctrl@f000000 {
		compatible = "qcom,parrot-vm-tlmm";
		gpios = /bits/ 16 <98 99 10 11 12 13 64 65>;

		qupv3_se11_i2c_active: qupv3_se11_i2c_sda_active {
			mux {
				pins = "gpio10";
				function = "qup1_se3_l0";
			};

			config {
				pins = "gpio10";
				drive-strength = <2>;
				bias-pull-up;
			};
		};

		qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
			mux {
				pins = "gpio10";
				function = "gpio";
			};

			config {
				pins = "gpio10";
				drive-strength = <2>;
			};
		};
	};

	tlmm-vm-test {
		pinctrl-names = "active", "sleep";
		pinctrl-0 = <&qupv3_se11_i2c_active>;
		pinctrl-1 = <&qupv3_se11_i2c_sleep>;
		tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0 &tlmm 10 0 &tlmm 11 0
			&tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>;
	};

	tlmm-vm-mem-access {
		tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0 &tlmm 10 0 &tlmm 11 0
			&tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>;
	};

	apps-smmu@15000000 {
		qcom,actlr =
			/* Display and camera clients, +0 PF */
			<0x800 0x7ff 0x1>,
			<0x2000 0xE0 0x1>,
			<0x2100 0x60 0x1>,
			/* For video clients, +3 PF */
			<0x2180 0x27 0x103>,
			/* NSP clients, +15PF */
			<0x1000 0x7ff 0x303>;
	};

	/delete-node/ qup_common_iommu_group;
	/delete-node/ qcom,qupv3_0_geni_se@9c0000;
	/delete-node/ qcom,gpi-dma@900000;
	/delete-node/ i2c@990000;
	/delete-node/ spi@990000;

	qup_iommu_group: qup_common_iommu_group {
			iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>,
					<&qupv3_1 0x00000000 0x00020000>;
	};

	gpi_dma1: qcom,gpi-dma@a00000  {
		compatible = "qcom,gpi-dma";
		#dma-cells = <5>;
		reg = <0xa00000  0x60000>;
		reg-names = "gpi-top";
		iommus = <&apps_smmu 0x418 0x0>;
		qcom,iommu-group = <&qup_iommu_group>;
		memory-region = <&qup_iommu_group>;
		dma-coherent;
		interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
		qcom,max-num-gpii = <12>;
		qcom,gpii-mask = <0x40>;
		qcom,ev-factor = <2>;
		qcom,gpi-ee-offset = <0x10000>;
		qcom,le-vm;
		status = "ok";
	};

	/* QUPv3_1 wrapper instance */
	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
		compatible = "qcom,geni-se-qup";
		reg = <0xac0000 0x2000>;
		#address-cells = <1>;
		#size-cells = <1>;
		clock-names = "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		iommus = <&apps_smmu 0x418 0x0>;
		qcom,iommu-group = <&qup_iommu_group>;
		memory-region = <&qup_iommu_group>;
		dma-coherent;
		ranges;
		status = "ok";

		/* TUI over I2C */
		qupv3_se9_i2c: i2c@a8c000 {
			compatible = "qcom,i2c-geni";
			reg = <0xa8c000 0x4000>;
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&gpi_dma1 0 3 3 64 0>,
				<&gpi_dma1 1 3 3 64 0>;
			dma-names = "tx", "rx";
			qcom,le-vm;
			status = "disabled";
		};

		qupv3_se9_spi: spi@a8c000 {
			compatible = "qcom,spi-geni";
			reg = <0xa8c000 0x4000>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg-names = "se_phys";
			dmas = <&gpi_dma1 0 3 1 64 0>,
				<&gpi_dma1 1 3 1 64 0>;
			dma-names = "tx", "rx";
			spi-max-frequency = <50000000>;
			qcom,le-vm;
			status = "disabled";
		};
	};


};