9b090db434
Add devicetree nodes to enable qmp communication with aop and tme. Change-Id: I4e30e6854fcb1d29ea3733d9d59bb01acfe6667b Signed-off-by: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
728 lines
16 KiB
Plaintext
728 lines
16 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
|
|
/*
|
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
|
|
#include <dt-bindings/clock/qcom,cambistmclkcc-sun.h>
|
|
#include <dt-bindings/clock/qcom,camcc-sun.h>
|
|
#include <dt-bindings/clock/qcom,dispcc-tuna.h>
|
|
#include <dt-bindings/clock/qcom,gcc-kera.h>
|
|
#include <dt-bindings/clock/qcom,gpucc-kera.h>
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
|
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
|
|
#include <dt-bindings/clock/qcom,videocc-tuna.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
|
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
|
|
|
/ {
|
|
model = "Qualcomm Technologies, Inc. Kera";
|
|
compatible = "qcom,kera";
|
|
qcom,msm-id = <659 0x10000>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0 0 0 0>;
|
|
};
|
|
|
|
chosen: chosen {
|
|
bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
|
|
};
|
|
|
|
reserved_memory: reserved-memory {};
|
|
|
|
firmware: firmware {
|
|
qcom_scm: qcom_scm { };
|
|
};
|
|
|
|
aliases {};
|
|
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
CPU0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "spin-table"; /* TODO: Update to psci */
|
|
cpu-release-addr = <0x0 0xE3940000>;
|
|
next-level-cache = <&L2_0>;
|
|
L2_0: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
|
|
L3_0: l3-cache {
|
|
compatible = "cache";
|
|
cache-level = <3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
CPU1: cpu@100 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x100>;
|
|
enable-method = "spin-table"; /* TODO: Update to psci */
|
|
cpu-release-addr = <0x0 0xE3940000>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
|
|
CPU2: cpu@200 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x200>;
|
|
enable-method = "spin-table"; /* TODO: Update to psci */
|
|
cpu-release-addr = <0x0 0xE3940000>;
|
|
next-level-cache = <&L2_2>;
|
|
L2_2: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
};
|
|
|
|
CPU3: cpu@300 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x300>;
|
|
enable-method = "spin-table"; /* TODO: Update to psci */
|
|
cpu-release-addr = <0x0 0xE3940000>;
|
|
next-level-cache = <&L2_3>;
|
|
L2_3: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
};
|
|
|
|
CPU4: cpu@400 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x400>;
|
|
enable-method = "spin-table"; /* TODO: Update to psci */
|
|
cpu-release-addr = <0x0 0xE3940000>;
|
|
next-level-cache = <&L2_4>;
|
|
L2_4: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
};
|
|
|
|
CPU5: cpu@500 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x500>;
|
|
enable-method = "spin-table"; /* TODO: Update to psci */
|
|
cpu-release-addr = <0x0 0xE3940000>;
|
|
next-level-cache = <&L2_5>;
|
|
L2_5: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
};
|
|
|
|
CPU6: cpu@600 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x600>;
|
|
enable-method = "spin-table"; /* TODO: Update to psci */
|
|
cpu-release-addr = <0x0 0xE3940000>;
|
|
next-level-cache = <&L2_6>;
|
|
L2_6: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
};
|
|
|
|
CPU7: cpu@700 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x700>;
|
|
enable-method = "spin-table"; /* TODO: Update to psci */
|
|
cpu-release-addr = <0x0 0xE3940000>;
|
|
next-level-cache = <&L2_7>;
|
|
L2_7: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
};
|
|
|
|
cpu-map {
|
|
cluster0 {
|
|
core0 {
|
|
cpu = <&CPU0>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <&CPU1>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <&CPU2>;
|
|
};
|
|
};
|
|
|
|
cluster1 {
|
|
core0 {
|
|
cpu = <&CPU3>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <&CPU4>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <&CPU5>;
|
|
};
|
|
|
|
core3 {
|
|
cpu = <&CPU6>;
|
|
};
|
|
};
|
|
|
|
cluster2 {
|
|
core0 {
|
|
cpu = <&CPU7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
soc: soc { };
|
|
};
|
|
|
|
&firmware {
|
|
qcom_scm {
|
|
compatible = "qcom,scm";
|
|
qcom,dload-mode = <&tcsr 0x19000>;
|
|
};
|
|
|
|
qtee_shmbridge {
|
|
compatible = "qcom,tee-shared-memory-bridge";
|
|
};
|
|
};
|
|
|
|
#include "kera-reserved-memory.dtsi"
|
|
#include "msm-arm-smmu-kera.dtsi"
|
|
#include "kera-dma-heaps.dtsi"
|
|
|
|
&reserved_memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
/* global autoconfigured region for contiguous allocations */
|
|
system_cma: linux,cma {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x2000000>;
|
|
linux,cma-default;
|
|
};
|
|
};
|
|
|
|
&soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
|
|
intc: interrupt-controller@17100000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x40000>;
|
|
reg = <0x17100000 0x10000>, /* GICD */
|
|
<0x17180000 0x200000>; /* GICR * 8 */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
arch_timer: timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
memtimer: timer@17420000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17420000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@17421000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17421000 0x1000>,
|
|
<0x17422000 0x1000>;
|
|
};
|
|
|
|
frame@17423000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17423000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17425000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17425000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17427000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17427000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17429000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17429000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742b000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x1742b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742d000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x1742d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
apps_rsc: rsc@17a00000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x17a00000 0x10000>,
|
|
<0x17a10000 0x10000>,
|
|
<0x17a20000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
qcom,drv-count = <3>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
apps_rsc_drv2: drv@2 {
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,tcs-distance = <0x2a0>;
|
|
channel@0 {
|
|
qcom,tcs-config = <ACTIVE_TCS 3>,
|
|
<SLEEP_TCS 2>,
|
|
<WAKE_TCS 2>,
|
|
<CONTROL_TCS 0>,
|
|
<FAST_PATH_TCS 1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
disp_rsc: rsc@af20000 {
|
|
label = "disp_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xaf20000 0x1000>;
|
|
reg-names = "drv-0";
|
|
qcom,drv-count = <1>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
disp_rsc_drv0: drv@0 {
|
|
qcom,drv-id = <0>;
|
|
qcom,tcs-offset = <0x520>;
|
|
qcom,tcs-distance = <0x150>;
|
|
channel@0 {
|
|
qcom,tcs-config = <ACTIVE_TCS 0>,
|
|
<SLEEP_TCS 1>,
|
|
<WAKE_TCS 1>,
|
|
<CONTROL_TCS 0>,
|
|
<FAST_PATH_TCS 0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,kera-pdc", "qcom,pdc";
|
|
reg = <0xb220000 0x10000>, <0x17c000f0 0x60>;
|
|
qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>,
|
|
<10 230 1>, <11 724 1>, <12 716 1>,
|
|
<13 727 1>, <14 720 1>, <15 726 1>,
|
|
<16 721 1>, <17 262 1>, <18 70 1>,
|
|
<19 723 1>, <20 234 1>, <22 725 1>,
|
|
<23 231 1>, <24 504 5>, <30 510 8>,
|
|
<40 520 6>, <51 531 4>, <58 538 2>,
|
|
<61 541 5>, <66 92 1>, <67 547 13>,
|
|
<80 240 1>, <81 235 1>, <82 310 2>,
|
|
<84 248 1>, <85 241 1>, <86 238 2>,
|
|
<88 254 1>, <89 509 1>, <90 563 1>,
|
|
<91 259 2>, <93 201 1>, <94 246 1>,
|
|
<95 93 1>, <96 611 29>, <125 63 1>,
|
|
<126 366 2>, <128 374 1>, <129 377 1>,
|
|
<130 428 1>, <131 434 2>, <133 437 1>,
|
|
<134 452 2>, <136 458 2>, <138 464 11>,
|
|
<149 671 1>, <150 688 1>, <151 714 2>,
|
|
<153 722 1>, <154 255 1>, <155 269 2>,
|
|
<157 276 1>, <158 287 1>, <159 306 4>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
tlmm: pinctrl@f000000 {
|
|
compatible = "qcom,kera-tlmm";
|
|
reg = <0xf000000 0x1000000>;
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
wakeup-parent = <&pdc>;
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
ipcc_mproc: qcom,ipcc@406000 {
|
|
compatible = "qcom,ipcc";
|
|
reg = <0x406000 0x1000>;
|
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
aoss_qmp: power-controller@c300000 {
|
|
compatible = "qcom,aoss-qmp";
|
|
reg = <0xc300000 0x400>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
#power-domain-cells = <1>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,qmp = <&aoss_qmp>;
|
|
label = "aop";
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
qmp_tme: qcom,qmp-tme {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,remote-pid = <14>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_TME
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "tme_qmp";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_TME
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "tme";
|
|
qcom,early-boot;
|
|
priority = <0>;
|
|
mbox-desc-offset = <0x0>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
cache-controller@24800000 {
|
|
compatible = "qcom,kera-llcc";
|
|
reg = <0x24800000 0x200000>, <0x24C00000 0x200000>,
|
|
<0x26800000 0x200000>, <0x26C00000 0x200000>;
|
|
reg-names = "llcc0_base", "llcc2_base",
|
|
"llcc_broadcast_or_base", "llcc_broadcast_and_base";
|
|
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
|
|
cap-based-alloc-and-pwr-collapse;
|
|
};
|
|
|
|
tcsr: syscon@1fc0000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fc0000 0x30000>;
|
|
};
|
|
|
|
eud: qcom,msm-eud@88e0000 {
|
|
compatible = "qcom,msm-eud";
|
|
interrupt-names = "eud_irq";
|
|
interrupt-parent = <&pdc>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x88e0000 0x2000>,
|
|
<0x88e2000 0x1000>;
|
|
reg-names = "eud_base", "eud_mode_mgr2";
|
|
qcom,secure-eud-en;
|
|
qcom,eud-utmi-delay = /bits/ 16 <255>;
|
|
status = "ok";
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo_board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <76800000>;
|
|
clock-output-names = "xo_board";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sleep_clk: sleep_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "sleep_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_0_pipe_clk: pcie_0_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_1_pipe_clk: pcie_1_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_1_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_rx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_rx_symbol_1_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_tx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "fixed-clock";
|
|
clock-output-names = "rpmh_clocks";
|
|
clock-frequency = <19200000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
cambistmclkcc: clock-controller@1760000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "cambistmclkcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
camcc: clock-controller@ade0000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "camcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "dispcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "gcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpucc: clock-controller@3d90000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "gpucc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
tcsrcc: clock-controller@1f40000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "tcsrcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
videocc: clock-controller@aaf0000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "videocc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
#include "tuna-gdsc.dtsi"
|
|
|
|
&cam_cc_ipe_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&cam_cc_ofe_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&cam_cc_tfe_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&cam_cc_tfe_1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&cam_cc_tfe_2_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&cam_cc_titan_top_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&disp_cc_mdss_core_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&disp_cc_mdss_core_int2_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_pcie_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_pcie_0_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_pcie_1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_pcie_1_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_ufs_mem_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_ufs_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_usb30_prim_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_usb3_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_cc_cx_gdsc_hw_ctrl {
|
|
reg = <0x3d99124 0x4>;
|
|
};
|
|
|
|
&gpu_cc_cx_gdsc {
|
|
compatible = "regulator-fixed";
|
|
reg = <0x3d99110 0x4>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_cc_gx_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&video_cc_mvs0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&video_cc_mvs0c_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&reserved_memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
aop_cmd_db_mem: aop_cmd_db_region@81c60000 {
|
|
compatible = "qcom,cmd-db";
|
|
no-map;
|
|
reg = <0x0 0x81c60000 0x0 0x20000>;
|
|
};
|
|
};
|
|
|
|
#include "kera-pinctrl.dtsi"
|
|
#include "kera-usb.dtsi"
|