6872575b92
Add the compatible for X1E80100 platforms. Change-Id: I48890af9ec1d5ac6c8cf38b35e63a8f67f842896 Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
111 lines
2.9 KiB
YAML
111 lines
2.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Last Level Cache Controller
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maintainers:
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- Rishabh Bhatnagar <rishabhb@codeaurora.org>
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- Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
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description: |
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LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
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that can be shared by multiple clients. Clients here are different cores in the
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SoC, the idea is to minimize the local caches at the clients and migrate to
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common pool of memory. Cache memory is divided into partitions called slices
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which are assigned to clients. Clients can query the slice details, activate
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and deactivate them.
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properties:
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compatible:
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enum:
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- qcom,sc7180-llcc
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- qcom,sc7280-llcc
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- qcom,sc8180x-llcc
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- qcom,sc8280xp-llcc
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- qcom,sdm845-llcc
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- qcom,sm6350-llcc
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- qcom,sm8150-llcc
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- qcom,sm8250-llcc
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- qcom,sm8350-llcc
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- qcom,sm8450-llcc
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- qcom,sm8550-llcc
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- qcom,pineapple-llcc
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- qcom,sun-llcc
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- qcom,x1e80100-llcc
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reg:
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minItems: 2
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maxItems: 9
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reg-names:
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minItems: 2
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maxItems: 9
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interrupts:
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maxItems: 1
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child-node:
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description: Container of llcc_perfmon node
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type: object
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properties:
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compatible:
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const: qcom,llcc-perfmon
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required:
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- compatible
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- reg
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- reg-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pineapple-llcc
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- qcom,sun-llcc
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- qcom,x1e80100-llcc
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then:
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properties:
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reg:
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items:
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- description: LLCC0 base register region
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- description: LLCC1 base register region
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- description: LLCC2 base register region
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- description: LLCC3 base register region
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- description: LLCC broadcast base register region
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reg-names:
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items:
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- const: llcc0_base
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- const: llcc1_base
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- const: llcc2_base
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- const: llcc3_base
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- const: llcc_broadcast_base
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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system-cache-controller@1100000 {
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compatible = "qcom,sdm845-llcc";
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reg = <0x01100000 0x50000>, <0x01180000 0x50000>,
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<0x01200000 0x50000>, <0x01280000 0x50000>,
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<0x1300000 0x50000> ;
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reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
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"llcc3_base", "llcc_broadcast_base";
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interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
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llcc_perfmon {
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compatible = "qcom,llcc-perfmon";
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}
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};
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};
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