2678eeb8f6
Having S4J enabled in the TCS by default will cause TCS address to be populated with the wrong address on V8 and will cause TCS ACK hang. Thus, AOP will keep S4J and S5F regulators disabled by default and host will vote to enable S4J and S5F regulators based on V6 or V8 power grid, respectively. Change-Id: I852ca4aa80ef0e6bd5c802e6032f876fb53c9670 CRs-Fixed: 3709995
170 lines
3.9 KiB
Plaintext
170 lines
3.9 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interconnect/qcom,sun.h>
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&tlmm {
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cnss_pins {
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cnss_wlan_en_active: cnss_wlan_en_active {
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mux {
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pins = "gpio16";
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function = "gpio";
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};
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config {
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pins = "gpio16";
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drive-strength = <16>;
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output-high;
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bias-pull-up;
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};
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};
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cnss_wlan_en_sleep: cnss_wlan_en_sleep {
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mux {
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pins = "gpio16";
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function = "gpio";
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};
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config {
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pins = "gpio16";
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drive-strength = <2>;
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output-low;
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bias-pull-down;
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};
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};
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cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
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mux {
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pins = "gpio18";
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function = "wcn_sw_ctrl";
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};
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};
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cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
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mux {
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pins = "gpio19";
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function = "wcn_sw";
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};
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};
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cnss_host_sol_default: cnss_host_sol_default {
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mux {
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pins = "gpio202";
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function = "gpio";
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};
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config {
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pins = "gpio202";
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drive-strength = <4>;
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bias-pull-down;
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};
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};
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cnss_dev_sol_default: cnss_dev_sol_default {
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mux {
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pins = "gpio203";
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function = "gpio";
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};
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config {
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pins = "gpio203";
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drive-strength = <4>;
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bias-pull-down;
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};
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};
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};
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};
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&reserved_memory {
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cnss_wlan_mem: cnss_wlan_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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};
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};
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&soc {
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wlan_peach: qcom,cnss-peach@b0000000 {
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compatible = "qcom,cnss-peach";
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reg = <0xb0000000 0x10000>;
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reg-names = "smmu_iova_ipa";
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qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
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supported-ids = <0x110E>;
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wlan-en-gpio = <&tlmm 16 0>;
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qcom,bt-en-gpio = <&pm8550vs_f_gpios 3 0>;
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qcom,sw-ctrl-gpio = <&tlmm 18 0>;
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wlan-host-sol-gpio = <&tlmm 202 0>;
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wlan-dev-sol-gpio = <&tlmm 203 0>;
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/* List of GPIOs to be setup for interrupt wakeup capable */
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mpm_wake_set_gpios = <18 19>;
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pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
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"sw_ctrl_wl_cx", "sol_default";
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pinctrl-0 = <&cnss_wlan_en_active>;
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pinctrl-1 = <&cnss_wlan_en_sleep>;
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pinctrl-2 = <&cnss_wlan_sw_ctrl>;
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pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
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pinctrl-4 = <&cnss_host_sol_default &cnss_dev_sol_default>;
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qcom,wlan;
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qcom,wlan-rc-num = <0>;
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qcom,wlan-ramdump-dynamic = <0x780000>;
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cnss-enable-self-recovery;
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qcom,wlan-cbc-enabled;
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use-pm-domain;
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qcom,same-dt-multi-dev;
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/* For AOP communication, use direct QMP instead of mailbox */
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qcom,qmp = <&aoss_qmp>;
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msix-match-addr = <0x3000>;
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vdd-wlan-io-supply = <&L3F>;
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qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
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vdd-wlan-io12-supply = <&L2F>;
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qcom,vdd-wlan-io12-config = <1200000 1200000 0 0 1>;
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vdd-wlan-aon-supply = <&S4D>;
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qcom,vdd-wlan-aon-config = <876000 1036000 0 0 1>;
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vdd-wlan-dig-supply = <&S4J>;
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qcom,vdd-wlan-dig-config = <876000 1000000 0 0 1>;
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vdd-wlan-rfa1-supply = <&S3G>;
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qcom,vdd-wlan-rfa1-config = <1860000 2000000 0 0 1>;
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vdd-wlan-rfa2-supply = <&S7I>;
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qcom,vdd-wlan-rfa2-config = <1312000 1340000 0 0 1>;
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vdd-wlan-ant-share-supply = <&L6K>;
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qcom,vdd-wlan-ant-share-config = <1800000 1860000 0 0 1>;
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qcom,pdc_init_table =
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"{class: wlan_pdc, ss: rf, res: s4j.m, enable: 1}",
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"{class: wlan_pdc, ss: rf, res: s4j.v, enable: 1}",
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"{class: wlan_pdc, ss: rf, res: s4j.v, upval: 876}",
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"{class: wlan_pdc, ss: rf, res: s4j.v, dwnval: 876}";
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};
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};
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&pcie0_rp {
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#address-cells = <5>;
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#size-cells = <0>;
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cnss_pci0: cnss_pci0 {
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reg = <0 0 0 0 0>;
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qcom,iommu-group = <&cnss_pci_iommu_group0>;
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memory-region = <&cnss_wlan_mem>;
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#address-cells = <1>;
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#size-cells = <1>;
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cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
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qcom,iommu-msi-size = <0x1000>;
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qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
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qcom,iommu-geometry = <0xa0000000 0x10010000>;
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qcom,iommu-dma = "fastmap";
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qcom,iommu-pagetable = "coherent";
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qcom,iommu-faults = "stall-disable", "HUPCF",
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"non-fatal";
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};
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};
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};
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