01d92b6ef4
Add vcpu sched test msgq in TUIVM vdevice node to validate gunyah vcpu scheduling. Change-Id: I16c0d9e17d8421413e0ea4203e7a71834050f1b6 Signed-off-by: Meena Pasumarthi <quic_pasumart@quicinc.com>
354 lines
8.3 KiB
Plaintext
354 lines
8.3 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
|
|
/*
|
|
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
|
|
|
/ {
|
|
#address-cells = <0x2>;
|
|
#size-cells = <0x2>;
|
|
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
|
|
interrupt-parent = <&vgic>;
|
|
|
|
chosen {
|
|
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <0x2>;
|
|
#size-cells = <0x0>;
|
|
|
|
CPU0: cpu@0 {
|
|
compatible = "arm,armv8";
|
|
reg = <0x0 0x0>;
|
|
device_type = "cpu";
|
|
enable-method = "psci";
|
|
cpu-idle-states = <&CPU_PWR_DWN
|
|
&CLUSTER_PWR_DWN>;
|
|
};
|
|
|
|
CPU1: cpu@100 {
|
|
compatible = "arm,armv8";
|
|
reg = <0x0 0x100>;
|
|
device_type = "cpu";
|
|
enable-method = "psci";
|
|
cpu-idle-states = <&CPU_PWR_DWN
|
|
&CLUSTER_PWR_DWN>;
|
|
|
|
};
|
|
};
|
|
|
|
idle-states {
|
|
CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */
|
|
compatible = "arm,idle-state";
|
|
idle-state-name = "rail-pc";
|
|
entry-latency-us = <550>;
|
|
exit-latency-us = <1050>;
|
|
min-residency-us = <7951>;
|
|
arm,psci-suspend-param = <0x40000004>;
|
|
local-timer-stop;
|
|
status = "disabled";
|
|
};
|
|
|
|
CLUSTER_PWR_DWN: d4 { /* C4+D4 */
|
|
compatible = "arm,idle-state";
|
|
idle-state-name = "l3-pc";
|
|
entry-latency-us = <750>;
|
|
exit-latency-us = <2350>;
|
|
min-residency-us = <9144>;
|
|
arm,psci-suspend-param = <0x40000044>;
|
|
local-timer-stop;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qcom,vm-config {
|
|
compatible = "qcom,vm-1.0";
|
|
vm-type = "aarch64-guest";
|
|
boot-config = "fdt,unified";
|
|
os-type = "linux";
|
|
kernel-entry-segment = "kernel";
|
|
kernel-entry-offset = <0x0 0x0>;
|
|
vendor = "QTI";
|
|
image-name = "qcom,trustedvm";
|
|
qcom,pasid = <0x0 0x1c>;
|
|
qcom,qtee-config-info = "p=3,9,39,77,78,7C,8F,97,C8,FE,11B,159,199,47E,7F1,CDF;";
|
|
qcom,secdomain-ids = <45>;
|
|
qcom,primary-vm-index = <0>;
|
|
vm-uri = "vmuid/trusted-ui";
|
|
vm-guid = "598085da-c516-5b25-a9c1-927a02819770";
|
|
qcom,sensitive;
|
|
|
|
iomemory-ranges = <0x0 0x409000 0x0 0x409000 0x0 0x1000 0x0
|
|
0x0 0xa20000 0x0 0xa20000 0x0 0x4000 0x0
|
|
0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
|
|
0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
|
|
0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
|
|
0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1
|
|
0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1
|
|
0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;
|
|
|
|
/* For LEVM pored usecases is SE4 and SE7, for SE4 we used gpii4
|
|
* and irq no is 315, for SE7 we used gpii5 and irq no is 316.
|
|
*/
|
|
gic-irq-ranges = <101 101
|
|
315 315
|
|
316 316>; /* PVM->SVM IRQ transfer */
|
|
|
|
vm-attrs = "crash-fatal", "context-dump";
|
|
|
|
memory {
|
|
#address-cells = <0x2>;
|
|
#size-cells = <0x0>;
|
|
/*
|
|
* IPA address linux image is loaded at. Must be within
|
|
* first 1GB due to memory hotplug requirement.
|
|
*/
|
|
base-address = <0x0 0x28800000 >;
|
|
};
|
|
|
|
segments {
|
|
config_cpio = <2>;
|
|
};
|
|
|
|
vcpus {
|
|
config = "/cpus";
|
|
affinity = "proxy";
|
|
affinity-map = <0x5 0x6>;
|
|
sched-priority = <0>; /* relative to PVM */
|
|
sched-timeslice = <2000>; /* in ms */
|
|
};
|
|
|
|
interrupts {
|
|
config = &vgic;
|
|
};
|
|
|
|
vdevices {
|
|
generate = "/hypervisor";
|
|
|
|
rm-rpc {
|
|
vdevice-type = "rm-rpc";
|
|
generate = "/hypervisor/qcom,resource-mgr";
|
|
console-dev;
|
|
message-size = <0x000000f0>;
|
|
queue-depth = <0x00000008>;
|
|
qcom,label = <0x1>;
|
|
};
|
|
|
|
virtio-mmio@0 {
|
|
vdevice-type = "virtio-mmio";
|
|
generate = "/virtio-mmio";
|
|
peer-default;
|
|
vqs-num = <0x1>;
|
|
push-compatible = "virtio,mmio";
|
|
dma-coherent;
|
|
dma_base = <0x0 0x0>;
|
|
memory {
|
|
qcom,label = <0x11>; //for persist.img
|
|
#address-cells = <0x2>;
|
|
base = <0x0 0xDA6F8000>;
|
|
};
|
|
};
|
|
|
|
virtio-mmio@1 {
|
|
vdevice-type = "virtio-mmio";
|
|
generate = "/virtio-mmio";
|
|
peer-default;
|
|
vqs-num = <0x2>;
|
|
push-compatible = "virtio,mmio";
|
|
dma-coherent;
|
|
dma_base = <0x0 0x4000>;
|
|
memory {
|
|
qcom,label = <0x10>; //for system.img
|
|
#address-cells = <0x2>;
|
|
base = <0x0 0xDA6FC000>;
|
|
};
|
|
};
|
|
|
|
swiotlb-shm {
|
|
vdevice-type = "shm";
|
|
generate = "/swiotlb";
|
|
push-compatible = "swiotlb";
|
|
peer-default;
|
|
dma_base = <0x0 0x8000>;
|
|
memory {
|
|
qcom,label = <0x12>;
|
|
#address-cells = <0x2>;
|
|
base = <0x0 0xDA700000>;
|
|
};
|
|
};
|
|
|
|
mem-buf-message-queue-pair {
|
|
vdevice-type = "message-queue-pair";
|
|
generate = "/hypervisor/membuf-msgq-pair";
|
|
message-size = <0x000000f0>;
|
|
queue-depth = <0x00000008>;
|
|
peer-default;
|
|
qcom,label = <0x0000001>;
|
|
};
|
|
|
|
gpiomem0 {
|
|
vdevice-type = "iomem";
|
|
patch = "/soc/tlmm-vm-mem-access";
|
|
push-compatible = "qcom,tlmm-vm-mem-access";
|
|
peer-default;
|
|
memory {
|
|
qcom,label = <0x8>;
|
|
qcom,mem-info-tag = <0x3>;
|
|
allocate-base;
|
|
};
|
|
};
|
|
|
|
test-dbl-tuivm {
|
|
vdevice-type = "doorbell";
|
|
generate = "/hypervisor/test-dbl-tuivm";
|
|
qcom,label = <0x4>;
|
|
peer-default;
|
|
};
|
|
|
|
test-dbl-tuivm-source {
|
|
vdevice-type = "doorbell-source";
|
|
generate = "/hypervisor/test-dbl-tuivm-source";
|
|
qcom,label = <0x4>;
|
|
peer-default;
|
|
};
|
|
|
|
test-msgq-tuivm {
|
|
vdevice-type = "message-queue-pair";
|
|
generate = "/hypervisor/test-msgq-tuivm-pair";
|
|
message-size = <0xf0>;
|
|
queue-depth = <0x8>;
|
|
qcom,label = <0x4>;
|
|
peer-default;
|
|
};
|
|
|
|
vcpu-sched-test-msgq {
|
|
vdevice-type = "message-queue-pair";
|
|
generate = "/hypervisor/sched-test-msgq-pair";
|
|
message-size = <0xf0>;
|
|
queue-depth = <0x8>;
|
|
qcom,label = <0x8>;
|
|
peer-default;
|
|
};
|
|
};
|
|
};
|
|
|
|
firmware: firmware {
|
|
scm {
|
|
compatible = "qcom,scm";
|
|
};
|
|
};
|
|
|
|
soc: soc { };
|
|
};
|
|
|
|
&soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
|
|
vm_tlmm_irq: vm-tlmm-irq@0 {
|
|
compatible = "qcom,tlmm-vm-irq";
|
|
reg = <0x0 0x0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
tlmm: pinctrl@f000000 {
|
|
compatible = "qcom,pineapple-vm-pinctrl";
|
|
reg = <0x0F000000 0x1000000>;
|
|
interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
/* Valid pins */
|
|
gpios = /bits/ 16 <86 87 133 137 48 49 50 51 161 162 91 60 61 62 63 88>;
|
|
};
|
|
|
|
tlmm-vm-mem-access {
|
|
compatible = "qcom,tlmm-vm-mem-access";
|
|
tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 133 0 &tlmm 137 0 &tlmm 48 0
|
|
&tlmm 49 0 &tlmm 50 0 &tlmm 51 0 &tlmm 161 0 &tlmm 162 0
|
|
&tlmm 91 0 &tlmm 60 0 &tlmm 61 0 &tlmm 62 0 &tlmm 63 0
|
|
&tlmm 88 0>;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
vgic: interrupt-controller@17100000 {
|
|
compatible = "arm,gic-v3";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x3>;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x40000>;
|
|
reg = <0x17100000 0x10000>, /* GICD */
|
|
<0x17180000 0x100000>; /* GICR * 8 */
|
|
};
|
|
|
|
ipcc_mproc_ns1: qcom,ipcc@409000 {
|
|
compatible = "qcom,ipcc";
|
|
reg = <0x409000 0x1000>;
|
|
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
arch_timer: timer {
|
|
compatible = "arm,armv8-timer";
|
|
always-on;
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
qcom,mem-buf {
|
|
compatible = "qcom,mem-buf";
|
|
qcom,mem-buf-capabilities = "consumer";
|
|
qcom,vmid = <45>;
|
|
};
|
|
|
|
qcom,mem-buf-msgq {
|
|
compatible = "qcom,mem-buf-msgq";
|
|
};
|
|
|
|
virtio_mem_device {
|
|
compatible = "qcom,virtio-mem";
|
|
/* Must be memory_block_size_bytes() aligned */
|
|
qcom,max-size = <0x0 0x10000000>;
|
|
qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
|
|
qcom,block-size = <0x400000>;
|
|
};
|
|
|
|
qcom,test-dbl-tuivm {
|
|
compatible = "qcom,gh-dbl";
|
|
qcom,label = <0x4>;
|
|
};
|
|
|
|
qcom,test-msgq-tuivm {
|
|
compatible = "qcom,gh-msgq-test";
|
|
gunyah-label = <4>;
|
|
affinity = <0>;
|
|
};
|
|
|
|
qcom,gh-qtimer@17425000 {
|
|
compatible = "qcom,gh-qtmr";
|
|
reg = <0x17425000 0x1000>;
|
|
reg-names = "qtmr-base";
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "qcom,qtmr-intr";
|
|
qcom,secondary;
|
|
};
|
|
};
|
|
|
|
#include "msm-arm-smmu-pineapple-vm.dtsi"
|
|
#include "pineapple-vm-dma-heaps.dtsi"
|