6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
27 lines
828 B
Plaintext
27 lines
828 B
Plaintext
LogicoreIP designed compatible with Xilinx ZYNQ family.
|
|
-------------------------------------------------------
|
|
|
|
General concept
|
|
---------------
|
|
|
|
LogicoreIP design to provide the isolation between processing system
|
|
and programmable logic. Also provides the list of register set to configure
|
|
the frequency.
|
|
|
|
Required properties:
|
|
- compatible: shall be one of:
|
|
"xlnx,vcu"
|
|
"xlnx,vcu-logicoreip-1.0"
|
|
- reg : The base offset and size of the VCU_PL_SLCR register space.
|
|
- clocks: phandle for aclk and pll_ref clocksource
|
|
- clock-names: The identification string, "aclk", is always required for
|
|
the axi clock. "pll_ref" is required for pll.
|
|
Example:
|
|
|
|
xlnx_vcu: vcu@a0040000 {
|
|
compatible = "xlnx,vcu-logicoreip-1.0";
|
|
reg = <0x0 0xa0040000 0x0 0x1000>;
|
|
clocks = <&si570_1>, <&clkc 71>;
|
|
clock-names = "pll_ref", "aclk";
|
|
};
|