6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
74 lines
1.8 KiB
YAML
74 lines
1.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: i.MX8M DDR Controller
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maintainers:
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- Peng Fan <peng.fan@nxp.com>
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description:
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The DDRC block is integrated in i.MX8M for interfacing with DDR based
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memories.
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It supports switching between different frequencies at runtime but during
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this process RAM itself becomes briefly inaccessible so actual frequency
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switching is implemented by TF-A code which runs from a SRAM area.
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The Linux driver for the DDRC doesn't even map registers (they're included
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for the sake of "describing hardware"), it mostly just exposes firmware
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capabilities through standard Linux mechanism like devfreq and OPP tables.
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properties:
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compatible:
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items:
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- enum:
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- fsl,imx8mn-ddrc
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- fsl,imx8mm-ddrc
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- fsl,imx8mq-ddrc
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- const: fsl,imx8m-ddrc
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reg:
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maxItems: 1
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description:
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Base address and size of DDRC CTL area.
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This is not currently mapped by the imx8m-ddrc driver.
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: core
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- const: pll
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- const: alt
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- const: apb
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operating-points-v2: true
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opp-table:
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type: object
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required:
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- reg
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- compatible
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mm-clock.h>
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ddrc: memory-controller@3d400000 {
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compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
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reg = <0x3d400000 0x400000>;
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clock-names = "core", "pll", "alt", "apb";
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clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
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<&clk IMX8MM_DRAM_PLL>,
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<&clk IMX8MM_CLK_DRAM_ALT>,
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<&clk IMX8MM_CLK_DRAM_APB>;
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operating-points-v2 = <&ddrc_opp_table>;
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};
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