6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
117 lines
3.0 KiB
YAML
117 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: MediaTek Display Port Controller
|
|
|
|
maintainers:
|
|
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
|
- Jitao shi <jitao.shi@mediatek.com>
|
|
|
|
description: |
|
|
MediaTek DP and eDP are different hardwares and there are some features
|
|
which are not supported for eDP. For example, audio is not supported for
|
|
eDP. Therefore, we need to use two different compatibles to describe them.
|
|
In addition, We just need to enable the power domain of DP, so the clock
|
|
of DP is generated by itself and we are not using other PLL to generate
|
|
clocks.
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- mediatek,mt8195-dp-tx
|
|
- mediatek,mt8195-edp-tx
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
nvmem-cells:
|
|
maxItems: 1
|
|
description: efuse data for display port calibration
|
|
|
|
nvmem-cell-names:
|
|
const: dp_calibration_data
|
|
|
|
power-domains:
|
|
maxItems: 1
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
ports:
|
|
$ref: /schemas/graph.yaml#/properties/ports
|
|
properties:
|
|
port@0:
|
|
$ref: /schemas/graph.yaml#/properties/port
|
|
description: Input endpoint of the controller, usually dp_intf
|
|
|
|
port@1:
|
|
$ref: /schemas/graph.yaml#/$defs/port-base
|
|
unevaluatedProperties: false
|
|
description: Output endpoint of the controller
|
|
properties:
|
|
endpoint:
|
|
$ref: /schemas/media/video-interfaces.yaml#
|
|
unevaluatedProperties: false
|
|
properties:
|
|
data-lanes:
|
|
description: |
|
|
number of lanes supported by the hardware.
|
|
The possible values:
|
|
0 - For 1 lane enabled in IP.
|
|
0 1 - For 2 lanes enabled in IP.
|
|
0 1 2 3 - For 4 lanes enabled in IP.
|
|
minItems: 1
|
|
maxItems: 4
|
|
required:
|
|
- data-lanes
|
|
|
|
required:
|
|
- port@0
|
|
- port@1
|
|
|
|
max-linkrate-mhz:
|
|
enum: [ 1620, 2700, 5400, 8100 ]
|
|
description: maximum link rate supported by the hardware.
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupts
|
|
- ports
|
|
- max-linkrate-mhz
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/power/mt8195-power.h>
|
|
dptx@1c600000 {
|
|
compatible = "mediatek,mt8195-dp-tx";
|
|
reg = <0x1c600000 0x8000>;
|
|
power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
|
|
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
max-linkrate-mhz = <8100>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
dptx_in: endpoint {
|
|
remote-endpoint = <&dp_intf0_out>;
|
|
};
|
|
};
|
|
port@1 {
|
|
reg = <1>;
|
|
dptx_out: endpoint {
|
|
data-lanes = <0 1 2 3>;
|
|
};
|
|
};
|
|
};
|
|
};
|