7c24cb15cb
Add the Level Shifter's external feedback clock entry to support the SD card HS50 mode running at 50MHz. By default, the Sun platforms use the Level Shifter devices with external feedback clock signal connects back to the MSM in order for the HS50 mode to work at 50MHz. Without the external feedback clock, the HS50 mode works at reduced frequency at 37.5MHz. Change-Id: I56c61411d7f792a389fa85661fce7fa5074e2c9f Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
314 lines
7.5 KiB
Plaintext
314 lines
7.5 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include "sun-pmic-overlay.dtsi"
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#include "sun-thermal-overlay.dtsi"
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&soc {
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gpio_keys {
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compatible = "gpio-keys";
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label = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&key_vol_up_default>;
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vol_up {
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label = "volume_up";
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gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
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linux,input-type = <1>;
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linux,code = <KEY_VOLUMEUP>;
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gpio-key,wakeup;
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debounce,interval = <15>;
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linux,can-disable;
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};
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};
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};
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®ulator_ocp_notifier {
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periph-1c1-supply = <&L1B>;
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periph-1c2-supply = <&L2B>;
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periph-1c4-supply = <&L4B>;
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periph-1c5-supply = <&L5B>;
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periph-1c6-supply = <&L6B>;
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periph-1c7-supply = <&L7B>;
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periph-1c8-supply = <&L8B>;
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periph-1c9-supply = <&L9B>;
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periph-1ca-supply = <&L10B>;
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periph-1cb-supply = <&L11B>;
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periph-1cc-supply = <&L12B>;
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periph-1cd-supply = <&L13B>;
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periph-1ce-supply = <&L14B>;
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periph-1cf-supply = <&L15B>;
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periph-1d0-supply = <&L16B>;
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periph-1d1-supply = <&L17B>;
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periph-1e4-supply = <&BOB1>;
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periph-1e6-supply = <&BOB2>;
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periph-39b-supply = <&S1D>;
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periph-39e-supply = <&S2D_LEVEL>;
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periph-3a1-supply = <&S3D>;
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periph-3a4-supply = <&S4D>;
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periph-3a7-supply = <&S5D_LEVEL>;
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periph-3c1-supply = <&L1D>;
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periph-3c2-supply = <&L2D>;
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periph-3c3-supply = <&L3D>;
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periph-5aa-supply = <&S6F_LEVEL>;
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periph-5c1-supply = <&L1F>;
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periph-5c2-supply = <&L2F>;
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periph-5c3-supply = <&L3F>;
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periph-69b-supply = <&S1G>;
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periph-69e-supply = <&S2G_LEVEL>;
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periph-6a1-supply = <&S3G>;
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periph-6a4-supply = <&S4G>;
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periph-6a7-supply = <&S5G_LEVEL>;
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periph-6ad-supply = <&S7G_LEVEL>;
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periph-6c1-supply = <&L1G>;
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periph-6c2-supply = <&L2G>;
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periph-6c3-supply = <&L3G>;
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periph-89b-supply = <&S1I_LEVEL>;
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periph-8a1-supply = <&S3I_LEVEL>;
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periph-8a7-supply = <&S5I_LEVEL>;
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periph-8aa-supply = <&S6I_LEVEL>;
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periph-8ad-supply = <&S7I>;
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periph-8b0-supply = <&S8I>;
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periph-8c1-supply = <&L1I>;
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periph-8c2-supply = <&L2I>;
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periph-8c3-supply = <&L3I>;
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periph-99b-supply = <&S1J_LEVEL>;
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periph-99e-supply = <&S2J>;
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periph-9a1-supply = <&S3J>;
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periph-9a4-supply = <&S4J>;
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periph-9c1-supply = <&L1J>;
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periph-9c2-supply = <&L2J>;
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periph-9c3-supply = <&L3J_LEVEL>;
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periph-ac1-supply = <&L1K>;
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periph-ac2-supply = <&L2K>;
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periph-ac3-supply = <&L3K>;
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periph-ac4-supply = <&L4K>;
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periph-ac5-supply = <&L5K>;
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periph-ac6-supply = <&L6K>;
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periph-ac7-supply = <&L7K>;
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periph-c40-supply = <&L1M>;
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periph-c41-supply = <&L2M>;
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periph-c42-supply = <&L3M>;
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periph-c43-supply = <&L4M>;
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periph-c44-supply = <&L5M>;
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periph-c45-supply = <&L6M>;
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periph-c46-supply = <&L7M>;
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periph-d40-supply = <&L1N>;
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periph-d41-supply = <&L2N>;
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periph-d42-supply = <&L3N>;
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periph-d43-supply = <&L4N>;
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periph-d44-supply = <&L5N>;
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periph-d45-supply = <&L6N>;
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periph-d46-supply = <&L7N>;
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};
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&pm8550_switch0 {
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qcom,led-mask = <9>; /* Channels 1 & 4 */
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qcom,symmetry-en;
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};
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&pm8550_switch1 {
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qcom,led-mask = <6>; /* Channels 2 & 3 */
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qcom,symmetry-en;
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};
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&pm8550_switch2 {
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qcom,led-mask = <15>; /* All Channels */
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qcom,symmetry-en;
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};
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&pm8550_flash {
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status = "ok";
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};
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qmp-v4-sun";
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/* VDDA_UFS_CORE */
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vdda-phy-supply = <&pm_v6j_l1>;
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vdda-phy-max-microamp = <213000>;
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/*
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* Platforms supporting Gear 5 && Rate B require a different
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* voltage supply. Check the Power Grid document.
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*/
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vdda-phy-min-microvolt = <912000>;
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/* VDDA_UFS_0_1P2 */
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vdda-pll-supply = <&pm_v8g_l3>;
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vdda-pll-max-microamp = <18300>;
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/* Phy GDSC for VDD_MX, always on */
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vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
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/* Qref power supply, Refer Qref diagram */
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vdda-qref-supply = <&pm_v8i_l3>;
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vdda-qref-max-microamp = <64500>;
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/*
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* Refer to Sun's Power Grid Analysis document.
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* Add vote for REFGEN_VDD_A_0P9/VDD_A_PCIE_0_0P9 regulator.
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*/
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vdda-refgen-supply = <&pm_v6f_l1>;
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vdda-refgen-max-microamp = <206000>;
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status = "ok";
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};
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&ufshc_mem {
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vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
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vcc-supply = <&pm_humu_l17>;
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vcc-max-microamp = <1300000>;
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vccq-supply = <&pm_v8d_l1>;
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vccq-max-microamp = <1200000>;
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/* UFS Rst pin is always on. It is shared with VDD_PX14 */
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qcom,vddp-ref-clk-supply = <&pm_v8i_l2>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vccq-parent-supply = <&pm_v8i_s7>;
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qcom,vccq-parent-max-microamp = <210000>;
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qcom,vccq-proxy-vote-supply = <&pm_v8d_l1>;
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qcom,vccq-proxy-vote-max-microamp = <1200000>;
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reset-gpios = <&tlmm 215 GPIO_ACTIVE_LOW>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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status = "ok";
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};
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&sdhc_2 {
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status = "ok";
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vdd-supply = <&pm_humu_l9>;
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qcom,vdd-voltage-level = <2950000 2960000>;
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qcom,vdd-current-level = <0 800000>;
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vdd-io-supply = <&pm_humu_l8>;
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qcom,vdd-io-voltage-level = <1800000 2960000>;
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qcom,vdd-io-current-level = <0 22000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc2_on>;
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pinctrl-1 = <&sdc2_off>;
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cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
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resets = <&gcc GCC_SDCC2_BCR>;
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reset-names = "core_reset";
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/*
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* By default, the Sun reference platforms use Level Shifter
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* devices with its Feedback Clock signal connects to the MSM.
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* Without the external feedback clock, the HS50 mode works at
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* reduced frequency at 37.5MHz.
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*/
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qcom,uses_level_shifter;
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qcom,external-fb-clk;
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};
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&eusb2_phy0 {
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dummy-supply = <&pmih010x_eusb2_repeater>;
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usb-repeater = <&pmih010x_eusb2_repeater>;
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};
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&qupv3_se4_i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "ok";
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qcom,touch-active = "st,fts";
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st_fts@49 {
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compatible = "st,fts";
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reg = <0x49>;
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interrupt-parent = <&tlmm>;
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interrupts = <162 0x2008>;
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vdd-supply = <&L4B>;
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avdd-supply = <&L14B>;
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pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
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pinctrl-0 = <&ts_active>;
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pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
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st,irq-gpio = <&tlmm 162 0x2008>;
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st,irq-flags = <8>;
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st,reset-gpio = <&tlmm 161 0x00>;
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st,regulator_dvdd = "vdd";
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st,regulator_avdd = "avdd";
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st,touch-type = "primary";
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st,qts_en;
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qts,trusted-touch-mode = "vm_mode";
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qts,touch-environment = "pvm";
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qts,trusted-touch-type = "primary";
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qts,trusted-touch-spi-irq = <652>;
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qts,trusted-touch-io-bases = <0xa90000>;
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qts,trusted-touch-io-sizes = <0x1000>;
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qts,trusted-touch-vm-gpio-list = <&tlmm 48 0 &tlmm 49 0 &tlmm 50 0
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&tlmm 51 0 &tlmm 161 0 &tlmm 162 0x2008>;
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};
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};
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&qupv3_se15_i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "ok";
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qcom,touch-active = "st,fts2";
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st_fts@49 {
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compatible = "st,fts2";
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reg = <0x49>;
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interrupt-parent = <&tlmm>;
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interrupts = <88 0x2008>;
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vdd-supply = <&L4B>;
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avdd-supply = <&L14B>;
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pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
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pinctrl-0 = <&ts_active>;
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pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
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st,irq-gpio = <&tlmm 88 0x2008>;
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st,irq-flags = <8>;
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st,reset-gpio = <&tlmm 100 0x00>;
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st,regulator_dvdd = "vdd";
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st,regulator_avdd = "avdd";
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st,touch-type = "secondary";
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st,qts_en;
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qts,trusted-touch-mode = "vm_mode";
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qts,touch-environment = "pvm";
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qts,trusted-touch-type = "secondary";
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qts,trusted-touch-spi-irq = <670>;
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qts,trusted-touch-io-bases = <0x89c000>;
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qts,trusted-touch-io-sizes = <0x1000>;
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qts,trusted-touch-vm-gpio-list = <&tlmm 28 0 &tlmm 29 0 &tlmm 30 0
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&tlmm 31 0 &tlmm 100 0 &tlmm 88 0x2008>;
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};
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};
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&usb0 {
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usb-role-switch;
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port {
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usb_port0: endpoint {
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remote-endpoint = <&usb_port0_connector>;
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};
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};
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};
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&ucsi {
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connector {
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port {
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usb_port0_connector: endpoint {
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remote-endpoint = <&usb_port0>;
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};
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};
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};
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};
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