0b2389f72f
Add the rpm-smd and mpm devicetree bindings. Change-Id: I18ea19cc4c9f76dfc257c460ace5380792f5172c Signed-off-by: Raghavendra Kakarla <quic_rkakarla@quicinc.com>
70 lines
2.0 KiB
YAML
70 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm-legacy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MPM Interrupt Controller
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maintainers:
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- Raghavendra Kakarla <quic_rkakarla@quicinc.com>
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description:
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Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
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MSM Power Manager (MPM) that is in always-on domain. In addition to managing
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resources during sleep, the hardware also has an interrupt controller that
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monitors the interrupts when the system is asleep, wakes up the APSS when
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one of these interrupts occur and replays it to GIC interrupt controller
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after GIC becomes operational.
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properties:
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compatible:
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items:
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- enum:
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- "qcom,mpm-blair"
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- "qcom,mpm-holi"
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- "qcom,mpm-pitti"
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- "qcom,mpm-monaco"
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- const: qcom,mpm
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reg:
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minItems: 1
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items:
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- description: Specifies the base address and size of vMPM registers in RPM MSG RAM.
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- description: Specifies the address and size of MPM timer registers in RPM MSG RAM.
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- description: Timer frame register to read the aggregated time.
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'#interrupt-cells':
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const: 2
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interrupt-controller: true
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required:
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- compatible
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- reg
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- interrupts
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- '#interrupt-cells'
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- interrupt-controller
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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mpm: interrupt-controller@45f01b8 {
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compatible = "qcom,mpm", "qcom,mpm-blair";
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interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
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reg = <0x45f01b8 0x1000>,
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<0xb011008 0x4>, /* MSM_APCS_GCC_BASE 4K */
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<0xf121000 0x1000>; /* Timer Frame Register */
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reg-names = "vmpm", "ipc", "timer";
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interrupt-controller;
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interrupt-parent = <&intc>;
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interrupt-cells = <2>;
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};
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wake-device {
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interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>;
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};
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